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See Semifore at the

DAC 2012

June 3-7, 2012

Booth 2314

Spring 2012 CSRCompiler Evaluation Program

Semifore has a better methodology for address register management. Don't use costly-to-build, hard-to-maintain, non-compliant, custom scripts.  Instead, automatically  generate   RTL synthesis, verification, firmware headers and documentation from your control register / status register(CSR) description.

If you would like an evaluation of Semifore's CSRCompilerTM to streamline your ASIC/FPGA design, synthesis, verification and documentation methodology, please contact us  at (650) 960-0925 or info@semifore.com to start today.


 

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No One Ever Said Designing and Sharing

a 100,000 Register Address Map Would be Easy...

Until Now – CSRCompilerTM from Semifore


 

CSRCompilerTM from Semifore turns difficult register map sharing into a smooth, integrated process.    Complex system design today, including both system-on-chip (SoC) and  field programmable gate arrays (FPGA), requires sharing different views of your large register map with –  RTL designers, design verification test engineers, firmware engineers, and technical writers. Homegrown scripts fall far short in providing accurate, complete, and consistent generated views of your large register map; views that are critical  to all of these dependent engineers.  The path to tape out is difficult enough without having problems pop-up (and schedules slip) due to miscommunication and out-of-date design descriptions when changes are made to your address map.

Semifore's CSRCompiler™ handles more file formats and more control register/status register functionality than any other commercially available or in-house tool. We accept IP-XACT, SystemRDL and your proprietary formats and generate both industry standard output and  targeted output for all of your other engineers. Plus, we're fast.  Your 100,000 register design can be compiled in a few minutes, not overnight, allowing the quick sharing of multiple design iterations.  Beyond what is provided today, we are also directly involved in the ongoing work related to industry standards in this area.

CSRCompiler™ is an advanced software tool suite that helps specify, generate and manage the register address map of a design. Offering a single source for the specification of the control registers and status registers, this tool suite accurately generates the relevant views of the information for the hardware, verification, software and documentation teams.

For design verification of your IP-XACT, SystemRDL, or CSV register map, Semifore leads the industry in fully supporting the Accellera UVM ("Universal Verification Methodology") register class library. Semifore's  CSRCompiler™, automatically generates UVM register class definitions directly from any of the following formats: CSRSpecTM, Spirit SystemRDL, IEEE 1685 IP-XACT, and spreadsheet.  Semifore also supports OVM and VMM for the verification of control register and status register designs.



Status Register, Control Register, Address Map Formats:

 Generated     Output Views:

csrcompiler_chart500_ver2dkgray
Semifore CSRSpecTM Synthesizable RTL (Verilog or VHDL)
Spirit SystemRDL Interchange Standards (Spirit IPXACT XML, IEEE 1685 IP-XACT).
IEEE 1685/Spirit IP-XACT. Verification Classes definitions (Accellera UVM, OVM, VMM RALF)
Spreadsheet Macro definition headers (C, openVera, Verilog, VHDL)
Legacy Formats Data Structures (Perl)
Documentation (Dynamic HMTL, Word, Framemaker)

 

 

For a more detailed introduction to control status register management concepts and using a register manager tool to simplify the work and reduce errors please click here.

Semifore Inc. also provides services to help you transition your address mapping from legacy CSR tools to CSRCompiler.