Total Register Automation Methodology


CSRCompiler - a practical, productive standards-based environment

In a market niche that is seriously under-serviced by productivity tools, CSRCompiler brings a practical approach to standards and integrates design, verification, software and documentation teams with a single-source specification that auto-generates all their necessary views. And instantly regenerates them for each revision. It minimizes risk to projects, profit, customers and careers.

Making your life easier: simple design capture and starndardized, self-checking authoring; clean, standard RTL; 100% accurate documentation auto-generated in Word or Framemaker.

Our benefits include: consistent documentations; single-source spec that generates both RTL and Header files; early software access to the address map layout and features

Take advantage of: consistent documentation; a single-source spec that generates the SystemVerilog test bench register model and register information for the virtual prototype; shorthand of nets for backdoor paths

Always 100% accurate: 100% accurate documentation auto-generated in Word or Framemaker; generate multiple document views and/or formats from the same source