Author Archive
November 20th, 2008
The Semifore design verification team currently uses the Certess Certitude tool to qualify the test benches and test cases used within Semifore for quality assurance. The Semifore CSRCompiler product creates synthesizable RTL from a register address map specification, unit level test benches, and testcases to verify that the generated RTL has the specified hardware and software semantics. After considering many techniques, the Semifore design verification team chose the Certess Certitude tool to automate the verification effort and RTL quality. The Certess Certitude tool provides the verification team feedback without a large commitment of team resources. The feedback includes a quality measurement and a detailed list of areas that need additional work.
Initial Porting Experience
The Semifore team has an extensive regression suite that has been in operation for several years and is continually improved as gaps are discovered in the verification coverage. The Certess Certitude tool instruments the regression and reports uncovered faults. The initial porting effort was performed on the Verilog RTL generation and verification outputs of the CSRCompiler. The port involved adjusting the regression execution scripts, test benches and diagnostic Verilog files to conform to the Certess requirements. The changes to the regression scripts were minimal which included replacing the device under test, DUT, Verilog RTL files with the Certess instrumented Verilog RTL files.
A small amount of improvement is also required by the automatically generated test bench and the test case Verilog files. The Certess flow requires that the regression return explicit pass or fail status. If the Semifore regression suite does report explicit failure, it had initially assumed as an implicit pass status with a regression running to completion without failure. The verification Verilog files were updated to return an explicit pass status. The Semifore verification team considers this an improvement and a best practice in the verification environment.
Results
The Semifore verification team was encouraged that the initial fault coverage result was very high; however several uncovered faults were identified. Most of these uncovered faults involved gaps in the verification. Some of the faults required more cross team communication because it was unclear if the design specification, implementation, or verification was incorrect.
One example of a gap in the verification identified by Certess Certitude is an uncovered fault in the read value of unspecified bits in a software accessible register in the address map. The Semifore verification environment has extensive checking to make sure that data for each specified field in register returned by a software read transaction is correct. However, the data returned for any unspecified bits in a register was not checked by the test bench.
Some of the uncovered faults reported were not clear that the verification environment had missed something. These faults were related to grey areas in industry standards. One example is a bus protocol standard which specifies the read data bus must be valid during the read transaction clock cycle when the bus ready signal is asserted. This standard unfortunately does not specify what the read data bus should contain during the other clock cylces. This is a case where the RTL implementation has the choice of many correct behaviors. The Semifore verification environment tests the RTL bus protocol behavior against the industry standard. The Certess Certitude tool identified an uncovered fault in the RTL logic which drives zeros to the bus when valid data is not required. This result is useful to Semifore because it identifies an area in the design that needs more analysis and discussion. Semifore now has the choice to disabling the fault in Certess Certitude, change the verification environment to match the RTL implementation, or change the RTL implementation. There is a value to identify grey areas in industry standards for design and verification teams since many grey areas are overlooked.
Semifore develops software for management of control and status registers. The entire product has been tested and fully functional with Certess Certitude tool. Semifore generates synthesizable RTL code with a test benches and diagnostic Verilog files. The Certess Certitude tool independently certify the quality of the test bench.
November 2nd, 2008
We completed some performance testing of the Semifore Compiler in September and I wanted to share some of the results with you. We translated the Intel I/O Controller Hub 9 (ICH9) Family Datasheet (downloaded from www.intel.com/assets/pdf/datasheet/316972.pdf ). This is a complex chip, often referred to as the Southbridge, which devotes more than 500 pages in the datasheet to documenting approximately 1,000 registers in the design. We used our jumpstart tools to translate the PDF into our input language, including field descriptions and generated a basic input file that was about 32,000 lines or 1.7MB of text.
Compiling and generating Verilog took about four seconds. And compiling and generating Verilog and a 500 page datasheet in WORD took about 7 seconds. We then took this as a building block and created a 5K, 10K, 20K, and 40K register design. Runtimes scaled linearly for compile and Verilog generation: 5K took 19 seconds, 10K took 38 seconds, 20K took 73 seconds, and 40K took about 155 seconds.
Memory usage ranged from 50Mb for the 1K example to 800Mb for the 40K example on a 32bit Pentium Processor. In these examples we were able to process about 250 registers a second and use about 24K of memory per register.
Summary for Compile and Generate Verilog
- 1K registers took 4 seconds and 50Mb of memory
- 5K registers took 19 seconds and 145Mb of memory
- 10K registers took 38 seconds and 241 Mb memory
- 20K registers took 73 seconds and 433 Mb memory
- 40K registers took 155 seconds and 815Mb of memory
Obviously this are just one set of examples, we would be happy to run a benchmark for you on your data and show you both our performance and the quality of our results. Please note that our use of the Intel example does not constitute an endorsement by Intel of our offering, it was simply the most complex example (from an address map perspective) that we could find that was diverse and well documented.
August 27th, 2008
As a part of our ongoing efforts to streamline design entry, Semifore now supports new and legacy designs using Excel spreadsheets as input. We have a full Error Correction Code example available on-line at http://www.semifore.com/products/ecc-example/. We have posted example output for Verilog, Word, HTML files, and verification test bench files.
Look for Semifore at EDA Tech Forum
See why Semifore is replacing internal scripts.
July 11th, 2008
We got an E-mail from Gary Delp thanking us for our review and feedback on the SystemRDL spec. We asked for and received Gary’s permission to share it on our blog.
“Semifore reviewed the SystemRDL spec in detail, and provided very helpful feedback for our June 2008 working group meeting. The feedback is helping us to focus our plans for attribute namespace management. I will be recommending that we include Semifore in the list of contributors to the draft standard, and will greatly appreciate your continued input into the work of the SPIRIT consortium.”
Gary Delp, Technical Director, The SPIRIT Consortium.
As a company, Semifore supports standards and is committed to solving our customers’ problems. We have been a member of the Spirit Consortium since 2006.
May 15th, 2008
Semifore today appointed Herbert Winsted to the position of director of business development. Mr. Winsted will be responsible for worldwide sales and support.
Semifore provides address maps for both new and legacy designs. Our single web-based source for your address map provides RTL, C and design documents views. Semifore provides accurate address maps as the design evolves. Semifore Inc was founded in 2006 to provide accurate specifications across functional teams.
“Mr. Winsted has broad global business experience, said Richard Weber, CEO of Semifore. “I’m confident that his experience with major account management will continue to create best practices that drive revenue growth.”
A 25-year EDA veteran, Mr. Winsted provided world wide sales and support for major accounts at Cadence Design, Silicon Valley Research, and Silvar-Lisco. He held various management positions at GEC Plessey Semiconductor and National Semiconductor. Mr. Winsted began his EDA career at Advanced Micro Devices, as a lead mask designer.
May 7th, 2008
Visit us at DAC Booth #681. See why Semiore is replacing internal tools for managing register address maps.
45th Annual Design Automation Conference
Anaheim, California
June 8 - 13, 2008
Imagine the whole design team working from a common control register specification viewable from a web page. We can work with you to import your existing register maps into CSRSpec. We may be able to fully or partially automate this process, depending upon your specific circumstances.
For DAC registration http://www.dac.com/45th/onlinereg.html
April 7th, 2008
Our partner Gary Stringham & Associates (www.garystringham.com) is presenting at the Embedded Systems Conference (www.cmp-egevents.com/web/esv/home), April 14-18, 2008, in San Jose, California, register now to attend either or both of these sessions that Gary will be presenting:
ESC-106 Best Practices in Hardware/Firmware Interface Design
Full-day tutorial: 8:30am - 4:30pm, Monday, April 14
Room: J1
ESC-346 Twenty-five Lessons Learned in Hardware/Firmware Interface Design
90-minute class: 2:00pm - 3:30pm, Wednesday, April 16
Room: J1
Another great source of information:
Their newsletter is a great source for best practices to bridge the hardware/ firmware divide. Documentation plays a key role in this effort since engineers must refer to it constantly to look up register and bit details. They have a number of time tested best practices on register documentation.
March 8th, 2008
Semifore and 74ze Engineering announced a strategic partnership today to provide services to import address maps for legacy design into Semifore’s register management solution. Once converted, Semifore’s CSRCompiler can manage register specifications in Verilog, C, and a variety of documentation outputs including HTML, Adobe FrameMaker, and Microsoft Word. A single input file eliminates wasted time debugging typos, searching for missing parameters, and reading stale specifications.
“We are pleased to select 74ze Engineering as a partner for design services,” said Richard Weber, CEO of Semifore. “74ze Engineering service offering makes it very easy for companies to reuse legacy IP blocks. Our customers value how they can now eliminate the multiple layers of scripts that were previously necessary to reuse the blocks.”
“Semifore’s CSRCompiler enables us to capture and reuse IP blocks easily,” said Peter Rohr, project manager and co-founder of 74ze Engineering. “Neither our engineers nor our clients need to spend days tracing through layers of scripts to ensure that the IP blocks are actually the same and can use the same software driver.”
“Semifore’s tool allows us to streamline a flow which would often waste engineering cycles fixing sloppy bugs and add a longer ramp-up time for newcomers to a project,” said Linc Jepson, CEO and co-founder of 74ze Engineering. “We can now offer a 48-hour import service that cleanly migrates a company to single-source, auto-generation of all of the files related to their register map: C-header files, register RTL code, and documentation. CSRCompiler is something we’ve seen a lot of companies burn a lot of internal engineering hours building and maintaining themselves.”
“With the partnership with Semifore, the CSR Compiler will be integrated into the jump start offering and included with a one-year right to use, so a customer can immediately use the blocks in their current design projects,” said Linc Jepson.
About 74ze Engineering www.74ze.com
74ze Engineering offer design and verifications services for ICs, FPGAs, and PCB development. With highly qualified teams of engineers in North America and Europe, 74ze offers strong experience in networking, DSPs, backplane development and signal integrity testing.
About Semifore www.semifore.com Semifore provides a single web-based source for your address map provides RTL, C and design documents views. Semifore provides accurate address maps as the design evolves. Semifore Inc was founded in 2006 to provide accurate specifications across functional teams.
March 2nd, 2008
Semifore will be exhibiting at DATE08, Europe’s largest event for the design, test, and manufacture of electronic systems and circuits.
Design, Automation, and Test in Europe
Munich, Germany
10-14 March, 2008
Semifore will be demonstrating the latest version of the CSR product tools for address map registers specification. A single web-based page for the Register Address Map eliminates wasted time debugging typos, missing parameters, and stale specifications. Come by and see us at booth B4.
February 15th, 2008
John McKenna has joined the Advisory Board of Semifore. As an advisor, Mr. McKenna will provide Semifore with strategic insight into the SOC semiconductor industry and provide direction for the company’s register address map platform.
Mr. McKenna has worked in a variety of roles in the last twenty-five years: director of engineering, director of software engineering, and director of customer support. Companies he has worked directly for include AMCC, MMC Networks, SVR and Amdahl.
“We are thrilled to have Mr. McKenna join our advisory board,” said Richard Weber, CEO of Semifore. “His experience growing successful teams for developing and supporting embedded software for complex processors and forging strong partnerships will help hit our next set of growth targets.”
“I have been impressed not only by my own evaluation of Semifore’s offering but by customer response,” McKenna observed. “Semifore has identified a much more powerful approach to keeping register specification in sync across hardware, software, and documentation teams collaborating on SOC designs. When you combine that with their commitment to current and emerging standards you have a solution that companies can embrace for higher productivity and fewer errors without fear of becoming stranded in a proprietary format.”
Semifore provides address maps for both new and legacy designs. Our single web-based source for your address map provides RTL (both Verilog and VHDL), C and design documents views. Semifore provides accurate address maps as the design evolves. Semifore Inc was founded in 2006 to provide accurate specifications across functional teams.
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