Semifore Releases Runtimes and Memory Usage

Add comment November 2nd, 2008

We completed some performance testing of the Semifore Compiler in September and I wanted to share some of the results with you. We translated the Intel I/O Controller Hub 9 (ICH9) Family Datasheet (downloaded from www.intel.com/assets/pdf/datasheet/316972.pdf ). This is a complex chip, often referred to as the Southbridge, which devotes more than 500 pages in the datasheet to documenting approximately 1,000 registers in the design. We used our jumpstart tools to translate the PDF into our input language, including field descriptions and generated a basic input file that was about 32,000 lines or 1.7MB of text.

Compiling and generating Verilog took about four seconds. And compiling and generating Verilog and a 500 page datasheet in WORD took about 7 seconds. We then took this as a building block and created a 5K, 10K, 20K, and 40K register design. Runtimes scaled linearly for compile and Verilog generation: 5K took 19 seconds, 10K took 38 seconds, 20K took 73 seconds, and 40K took about 155 seconds.

Memory usage ranged from 50Mb for the 1K example to 800Mb for the 40K example on a 32bit Pentium Processor. In these examples we were able to process about 250 registers a second and use about 24K of memory per register.

Summary for Compile and Generate Verilog

• 1K registers took 4 seconds and 50Mb of memory
• 5K registers took 19 seconds and 145Mb of memory
• 10K registers took 38 seconds and 241 Mb memory
• 20K registers took 73 seconds and 433 Mb memory
• 40K registers took 155 seconds and 815Mb of memory

Obviously this are just one set of examples, we would be happy to run a benchmark for you on your data and show you both our performance and the quality of our results. Please note that our use of the Intel example does not constitute an endorsement by Intel of our offering, it was simply the most complex example (from an address map perspective) that we could find that was diverse and well documented.

What Is A Mask?

Add comment July 3rd, 2008

The word mask has different meanings depending on your role in the design process. For many in the software development role a mask is a special value used to extract a set of bits from a larger quantity. For many in the hardware development role a mask is a quantity used to control the propagation of a signal.

In the software domain a developer writing code that interacts with hardware often finds the need to get at the value of a specific set of bits in a byte or word from the hardware. A special value called a mask is created to be an operand of an arithmetic AND operation with the byte or word obtained from the hardware. The result of the operation is a new quantity that can only have zeros in the undesired bit positions. If the quantity is considered a Boolean value it is ready to be used as a Boolean in several programming languages. Otherwise, the next operation is often a compare with zero or a right-shift operation to move the bits into the least significant bit positions. The mask is constructed by placing ones in the desired bit positions and zeros in the undesired bit positions.

In the hardware domain the designer may provide software control over the propagation of select signals. A common example of a signal that may need this control is an interrupt signal. The design provides a bit called a mask in a software accessible register to control the propagation of an interrupt up the interrupt hierarchy to its eventual destination at a CPU. The mask bit and the interrupt are both inputs to an AND gate in the interrupt hierarchy. Unfortunately, the presence of an INVERTER gate between the mask bit and the AND gate is not standardized. Both the hardware and software developers need to verify the required value of the mask bit that allows the propagation of the signal to correctly implement their solutions.