Events

 

Summer CSRCompiler Evaluation Program

Contact us to start today.

 

 



edatechforum

 

September 16, 2010
Santa Clara Convention Center
Santa Clara, CA

 


 

DVCon Expo

2011dvcon_expo_logo

 

March 1-2, 2011
DoubleTree Hotel
San Jose, CA

 

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No One Ever Said Designing and Sharing

a 40,000 Register Address Map Would be Easy...

Until Now – CSRCompilerTM from Semifore


 

CSRCompilerTM from Semifore turns difficult address map sharing into a smooth, integrated process.    Complex system design today, including both system-on-chip (SoC) and  field programmable gate arrays (FPGA), requires sharing different views of your large address map with –  RTL designers, design verification test engineers, firmware engineers, and technical writers. Homegrown scripts fall far short in providing accurate, complete, and consistent generated views of your large address map; views that are critical  to all of these dependent engineers.  The path to tape out is difficult enough without having problems pop-up (and schedules slip) due miscommunication and out-of-date design descriptions when changes are made to your address map.

Semifore's CSRCompiler™ handles more file formats and more register functionality than any other commerically available or in-house tool. We can accept your proprietary formats and generate both industry standard output and  targeted output for all of your other engineers. Plus, we're fast.  Your 40,000 register design can be compiled in a few minutes, not overnight, allowing the quick sharing of multiple design iterations.  Beyond what is provided today, we are also directly involved in the ongoing work related to industry standards in this area.

CSRCompiler™ is an advanced software tool suite that helps specify, generate and manage the register address map of a design. Offering a single source for the specification of the control and status registers, this tool suite accurately generates the relevant views of the information for the hardware, verification, software and documentation teams.


Address map formats: Generated     output views:

csrcompiler_chart500_ver2dkgray

Semifore CSRspecTM Synthesizable RTL (Verilog or VHDL)
Spirit SystemRDL Interchange Standards (Spirit IP-XACT XML, IEEE 1685)
Spirit ip_XACT xML, IEE 1685 Verification Classes definitions (VMM RALF)
Spreadsheet Macro definition headers (C, openVera, Verilog, VHDL)
Legacy formats Data Structures (Perl)
Documentation (Dynamic HMTL, Word, Framemaker)

 

 

For a more detailed introduction to basic register management concepts and using a tool to simplify the work and reduce errors please click here.

Semifore Inc. also provides services to help you transition from legacy tools to CSRCompiler.