/* WARNING for evaluation only. No Warranty expressed or implied. */ /* */ /* Generated by Semifore, Inc. csrCompile */ /* Version: 2008.03 */ /* Released on: Jul 23 2008 21:56:02 */ /* Verilog Header output */ /* */ /* Input file: ecc.csr */ /* version: 1.6 */ /* */ /* Generated on: Wed Jul 30 12:44:39 2008 */ /* by: weber */ /* */ `ifndef _ECC_VH_ `define _ECC_VH_ // ########################################################################## // ADDRESS MACROS // ########################################################################## // Address Space for Addressmap: ECC_regs // Source filename: ecc.csr, line: 335 // Register: ECC_regs.chip_config `define ECC_REGS__CHIP_CONFIG__ADDRESS 16'h0000 // Group: ECC_regs.pckt_mem_regs `define ECC_REGS__PCKT_MEM_REGS__ADDRESS 16'h0080 // Register: ECC_regs.pckt_mem_regs.ecc_cntrl_reg `define ECC_REGS__PCKT_MEM_REGS__ECC_CNTRL_REG__ADDRESS 16'h0080 // Register: ECC_regs.pckt_mem_regs.ecc_int_reg `define ECC_REGS__PCKT_MEM_REGS__ECC_INT_REG__ADDRESS 16'h0082 // Register: ECC_regs.pckt_mem_regs.ecc_int_en_reg `define ECC_REGS__PCKT_MEM_REGS__ECC_INT_EN_REG__ADDRESS 16'h0098 // Register: ECC_regs.pckt_mem_regs.int_cnt_reg `define ECC_REGS__PCKT_MEM_REGS__INT_CNT_REG__ADDRESS 16'h009a // Register: ECC_regs.pckt_mem_regs.ecc_err_addr_reg `define ECC_REGS__PCKT_MEM_REGS__ECC_ERR_ADDR_REG__ADDRESS 16'h009c // Register: ECC_regs.pckt_mem_regs.diag_cntrl_reg `define ECC_REGS__PCKT_MEM_REGS__DIAG_CNTRL_REG__ADDRESS 16'h009e // Register: ECC_regs.pckt_mem_regs.ecc_bits_reg `define ECC_REGS__PCKT_MEM_REGS__ECC_BITS_REG__ADDRESS 16'h00a0 // Register: ECC_regs.pckt_mem_regs.data_reg `define ECC_REGS__PCKT_MEM_REGS__DATA_REG__ADDRESS 16'h00c0 // Group: ECC_regs.rx_mem_regs `define ECC_REGS__RX_MEM_REGS__ADDRESS 16'h0200 `define ECC_REGS__RX_MEM_REGS__ARRAY_INDEX_MAX 64'h0000000000000003 `define ECC_REGS__RX_MEM_REGS__ARRAY_INDEX_MIN 64'h0000000000000000 `define ECC_REGS__RX_MEM_REGS__ARRAY_ELEMENT_SIZE 64'h0000000000000080 // Register: ECC_regs.rx_mem_regs.ecc_cntrl_reg `define ECC_REGS__RX_MEM_REGS__ECC_CNTRL_REG__ADDRESS 16'h0200 // Register: ECC_regs.rx_mem_regs.ecc_int_reg `define ECC_REGS__RX_MEM_REGS__ECC_INT_REG__ADDRESS 16'h0202 // Register: ECC_regs.rx_mem_regs.ecc_int_en_reg `define ECC_REGS__RX_MEM_REGS__ECC_INT_EN_REG__ADDRESS 16'h0218 // Register: ECC_regs.rx_mem_regs.int_cnt_reg `define ECC_REGS__RX_MEM_REGS__INT_CNT_REG__ADDRESS 16'h021a // Register: ECC_regs.rx_mem_regs.ecc_err_addr_reg `define ECC_REGS__RX_MEM_REGS__ECC_ERR_ADDR_REG__ADDRESS 16'h021c // Register: ECC_regs.rx_mem_regs.diag_cntrl_reg `define ECC_REGS__RX_MEM_REGS__DIAG_CNTRL_REG__ADDRESS 16'h021e // Register: ECC_regs.rx_mem_regs.ecc_bits_reg `define ECC_REGS__RX_MEM_REGS__ECC_BITS_REG__ADDRESS 16'h0220 // Register: ECC_regs.rx_mem_regs.data_reg `define ECC_REGS__RX_MEM_REGS__DATA_REG__ADDRESS 16'h0240 // Group: ECC_regs.tx_mem_regs `define ECC_REGS__TX_MEM_REGS__ADDRESS 16'h0400 `define ECC_REGS__TX_MEM_REGS__ARRAY_INDEX_MAX 64'h0000000000000003 `define ECC_REGS__TX_MEM_REGS__ARRAY_INDEX_MIN 64'h0000000000000000 `define ECC_REGS__TX_MEM_REGS__ARRAY_ELEMENT_SIZE 64'h0000000000000080 // Register: ECC_regs.tx_mem_regs.ecc_cntrl_reg `define ECC_REGS__TX_MEM_REGS__ECC_CNTRL_REG__ADDRESS 16'h0400 // Register: ECC_regs.tx_mem_regs.ecc_int_reg `define ECC_REGS__TX_MEM_REGS__ECC_INT_REG__ADDRESS 16'h0402 // Register: ECC_regs.tx_mem_regs.ecc_int_en_reg `define ECC_REGS__TX_MEM_REGS__ECC_INT_EN_REG__ADDRESS 16'h0418 // Register: ECC_regs.tx_mem_regs.int_cnt_reg `define ECC_REGS__TX_MEM_REGS__INT_CNT_REG__ADDRESS 16'h041a // Register: ECC_regs.tx_mem_regs.ecc_err_addr_reg `define ECC_REGS__TX_MEM_REGS__ECC_ERR_ADDR_REG__ADDRESS 16'h041c // Register: ECC_regs.tx_mem_regs.diag_cntrl_reg `define ECC_REGS__TX_MEM_REGS__DIAG_CNTRL_REG__ADDRESS 16'h041e // Register: ECC_regs.tx_mem_regs.ecc_bits_reg `define ECC_REGS__TX_MEM_REGS__ECC_BITS_REG__ADDRESS 16'h0420 // Register: ECC_regs.tx_mem_regs.data_reg `define ECC_REGS__TX_MEM_REGS__DATA_REG__ADDRESS 16'h0440 // Register: ECC_regs.pkt_memory `define ECC_REGS__PKT_MEMORY__ADDRESS 16'h8000 `define ECC_REGS__PKT_MEMORY__ARRAY_INDEX_MAX 64'h0000000000003fff `define ECC_REGS__PKT_MEMORY__ARRAY_INDEX_MIN 64'h0000000000000000 `define ECC_REGS__PKT_MEMORY__ARRAY_ELEMENT_SIZE 64'h0000000000000002 // ########################################################################## // TEMPLATE MACROS // ########################################################################## // Addressmap template: ECC_regs // Source filename: ecc.csr, line: 283 // Register instance: ECC_regs.chip_config // Register template referenced: ECC_regs::chip_config `define ECC_REGS__CHIP_CONFIG__OFFSET 16'h0000 `define ECC_REGS__CHIP_CONFIG__RESET_VALUE 16'h0000 `define ECC_REGS__CHIP_CONFIG__RESET_MASK 16'hffff `define ECC_REGS__CHIP_CONFIG__READ_ACCESS 1 `define ECC_REGS__CHIP_CONFIG__WRITE_ACCESS 1 `define ECC_REGS__CHIP_CONFIG__READ_MASK 16'hffff `define ECC_REGS__CHIP_CONFIG__WRITE_MASK 16'h0001 // Group instance: ECC_regs.pckt_mem_regs // Group template referenced: ecc_mem_reg_grp:address_bitwidth=14 `define ECC_REGS__PCKT_MEM_REGS__OFFSET 16'h0080 // Group instance: ECC_regs.rx_mem_regs // Group template referenced: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8 `define ECC_REGS__RX_MEM_REGS__OFFSET 16'h0200 // Group instance: ECC_regs.tx_mem_regs // Group template referenced: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8 `define ECC_REGS__TX_MEM_REGS__OFFSET 16'h0400 // Register instance: ECC_regs.pkt_memory // Register template referenced: ECC_regs::pkt_memory `define ECC_REGS__PKT_MEMORY__OFFSET 16'h8000 `define ECC_REGS__PKT_MEMORY__READ_ACCESS 1 `define ECC_REGS__PKT_MEMORY__WRITE_ACCESS 1 `define ECC_REGS__PKT_MEMORY__READ_MASK 16'hffff `define ECC_REGS__PKT_MEMORY__WRITE_MASK 16'hffff // Register template: ECC_regs::chip_config // Source filename: ecc.csr, line: 290 // Field instance: ECC_regs::chip_config.vpn_passthrough_enable `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__MSB 0 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__LSB 0 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__WIDTH 1 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__RANGE 0:0 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__READ_ACCESS 1 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__WRITE_ACCESS 1 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__RESET 1'h0 `define ECC_REGS__CHIP_CONFIG__VPN_PASSTHROUGH_ENABLE__MASK 16'h0001 // Group template: ecc_mem_reg_grp:address_bitwidth=14 // Source filename: ecc.csr, line: 41 // Register instance: ecc_mem_reg_grp:address_bitwidth=14.ecc_cntrl_reg // Register template referenced: ecc_mem_reg_grp::ecc_cntrl_reg:has_diagnostic_write=True `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__OFFSET 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__RESET_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_CNTRL_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=14.ecc_int_reg // Register template referenced: ecc_mem_reg_grp::ecc_int_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__OFFSET 16'h0002 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__RESET_MASK 16'hfffc `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=14.ecc_int_en_reg // Register template referenced: ecc_mem_reg_grp::ecc_int_en_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__OFFSET 16'h0018 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__RESET_MASK 16'hfffc `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_INT_EN_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=14.int_cnt_reg // Register template referenced: ecc_mem_reg_grp::int_cnt_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__INT_CNT_REG__OFFSET 16'h001a `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__INT_CNT_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__INT_CNT_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__INT_CNT_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__INT_CNT_REG__WRITE_MASK 16'hffff // Register instance: ecc_mem_reg_grp:address_bitwidth=14.ecc_err_addr_reg // Register template referenced: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=14 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__OFFSET 16'h001c `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__RESET_MASK 16'hc000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_ERR_ADDR_REG__WRITE_MASK 16'h3fff // Register instance: ecc_mem_reg_grp:address_bitwidth=14.diag_cntrl_reg // Register template referenced: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=14:has_diagnostic_read=True `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DIAG_CNTRL_REG__OFFSET 16'h001e `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DIAG_CNTRL_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DIAG_CNTRL_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DIAG_CNTRL_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DIAG_CNTRL_REG__WRITE_MASK 16'hffff // Register instance: ecc_mem_reg_grp:address_bitwidth=14.ecc_bits_reg // Register template referenced: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=6 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__OFFSET 16'h0020 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__RESET_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__ECC_BITS_REG__WRITE_MASK 16'h003f // Register instance: ecc_mem_reg_grp:address_bitwidth=14.data_reg // Register template referenced: ecc_mem_reg_grp::data_reg:data_bitwidth=16 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DATA_REG__OFFSET 16'h0040 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DATA_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DATA_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DATA_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__DATA_REG__WRITE_MASK 16'hffff // Register template: ecc_mem_reg_grp::ecc_cntrl_reg:has_diagnostic_write=True // Source filename: ecc.csr, line: 57 // Field instance: ecc_mem_reg_grp::ecc_cntrl_reg:has_diagnostic_write=True.diag_en `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__MSB 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__LSB 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__WIDTH 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__RANGE 1:1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__RESET 1'b0 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__DIAG_EN__MASK 16'h0002 // Field instance: ecc_mem_reg_grp::ecc_cntrl_reg:has_diagnostic_write=True.correct_en `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__MSB 0 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__LSB 0 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__WIDTH 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__RANGE 0:0 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__RESET 1'b0 `define ECC_MEM_REG_GRP__ECC_CNTRL_REG__HAS_DIAGNOSTIC_WRITE__TRUE__CORRECT_EN__MASK 16'h0001 // Register template: ecc_mem_reg_grp::ecc_int_reg // Source filename: ecc.csr, line: 98 // Field instance: ecc_mem_reg_grp::ecc_int_reg.sbe_int `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__MSB 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__LSB 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__WIDTH 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__RANGE 1:1 `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__SBE_INT__MASK 16'h0002 // Field instance: ecc_mem_reg_grp::ecc_int_reg.mbe_int `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__MSB 0 `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__LSB 0 `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__WIDTH 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__RANGE 0:0 `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_REG__MBE_INT__MASK 16'h0001 // Register template: ecc_mem_reg_grp::ecc_int_en_reg // Source filename: ecc.csr, line: 127 // Field instance: ecc_mem_reg_grp::ecc_int_en_reg.sbe_int_en `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__MSB 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__LSB 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__WIDTH 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__RANGE 1:1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__SBE_INT_EN__MASK 16'h0002 // Field instance: ecc_mem_reg_grp::ecc_int_en_reg.mbe_int_en `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__MSB 0 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__LSB 0 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__WIDTH 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__RANGE 0:0 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_INT_EN_REG__MBE_INT_EN__MASK 16'h0001 // Register template: ecc_mem_reg_grp::int_cnt_reg // Source filename: ecc.csr, line: 147 // Field instance: ecc_mem_reg_grp::int_cnt_reg.sbe_int_cnt `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__MSB 15 `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__LSB 8 `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__WIDTH 8 `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__RANGE 15:8 `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__READ_ACCESS 1 `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__INT_CNT_REG__SBE_INT_CNT__MASK 16'hff00 // Field instance: ecc_mem_reg_grp::int_cnt_reg.mbe_int_cnt `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__MSB 7 `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__LSB 0 `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__WIDTH 8 `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__RANGE 7:0 `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__READ_ACCESS 1 `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__INT_CNT_REG__MBE_INT_CNT__MASK 16'h00ff // Register template: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=14 // Source filename: ecc.csr, line: 169 // Field instance: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=14.address `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__MSB 13 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__LSB 0 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__WIDTH 14 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__RANGE 13:0 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__14__ADDRESS__MASK 16'h3fff // Register template: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=14:has_diagnostic_read=True // Source filename: ecc.csr, line: 190 // Field instance: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=14:has_diagnostic_read=True.initiate `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__MSB 15 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__LSB 15 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__WIDTH 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__RANGE 15:15 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__MASK 16'h8000 // Field instance: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=14:has_diagnostic_read=True.read `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__MSB 14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__LSB 14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__WIDTH 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__RANGE 14:14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__READ__MASK 16'h4000 // Field instance: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=14:has_diagnostic_read=True.diagnostic_address `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__MSB 13 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__LSB 0 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__WIDTH 14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__RANGE 13:0 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__14__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__MASK 16'h3fff // Register template: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=6 // Source filename: ecc.csr, line: 232 // Field instance: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=6.ecc_bits `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__MSB 5 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__LSB 0 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__WIDTH 6 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__RANGE 5:0 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__RESET 6'b000000 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__6__ECC_BITS__MASK 16'h003f // Register template: ecc_mem_reg_grp::data_reg:data_bitwidth=16 // Source filename: ecc.csr, line: 259 // Field instance: ecc_mem_reg_grp::data_reg:data_bitwidth=16.data_value `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__MSB 15 `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__LSB 0 `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__WIDTH 16 `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__RANGE 15:0 `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DATA_REG__DATA_BITWIDTH__16__DATA_VALUE__MASK 16'hffff // Group template: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8 // Source filename: ecc.csr, line: 41 // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.ecc_cntrl_reg // Register template referenced: ecc_mem_reg_grp::ecc_cntrl_reg:has_diagnostic_write=True `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__OFFSET 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__RESET_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.ecc_int_reg // Register template referenced: ecc_mem_reg_grp::ecc_int_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__OFFSET 16'h0002 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__RESET_MASK 16'hfffc `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.ecc_int_en_reg // Register template referenced: ecc_mem_reg_grp::ecc_int_en_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__OFFSET 16'h0018 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__RESET_MASK 16'hfffc `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.int_cnt_reg // Register template referenced: ecc_mem_reg_grp::int_cnt_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__INT_CNT_REG__OFFSET 16'h001a `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__INT_CNT_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__INT_CNT_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__INT_CNT_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__INT_CNT_REG__WRITE_MASK 16'hffff // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.ecc_err_addr_reg // Register template referenced: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=14 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__OFFSET 16'h001c `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__RESET_MASK 16'hc000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__WRITE_MASK 16'h3fff // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.diag_cntrl_reg // Register template referenced: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=14:has_diagnostic_read=True `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__OFFSET 16'h001e `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__WRITE_MASK 16'hffff // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.ecc_bits_reg // Register template referenced: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=8 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__OFFSET 16'h0020 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__RESET_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__ECC_BITS_REG__WRITE_MASK 16'h00ff // Register instance: ecc_mem_reg_grp:address_bitwidth=14:protection_bitwidth=8.data_reg // Register template referenced: ecc_mem_reg_grp::data_reg:data_bitwidth=16 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DATA_REG__OFFSET 16'h0040 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DATA_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DATA_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DATA_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__14__PROTECTION_BITWIDTH__8__DATA_REG__WRITE_MASK 16'hffff // Register template: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=8 // Source filename: ecc.csr, line: 232 // Field instance: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=8.ecc_bits `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__MSB 7 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__LSB 0 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__WIDTH 8 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__RANGE 7:0 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__RESET 8'b00000000 `define ECC_MEM_REG_GRP__ECC_BITS_REG__PROTECTION_BITWIDTH__8__ECC_BITS__MASK 16'h00ff // Group template: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8 // Source filename: ecc.csr, line: 41 // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.ecc_cntrl_reg // Register template referenced: ecc_mem_reg_grp::ecc_cntrl_reg:has_diagnostic_write=True `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__OFFSET 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__RESET_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_CNTRL_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.ecc_int_reg // Register template referenced: ecc_mem_reg_grp::ecc_int_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__OFFSET 16'h0002 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__RESET_MASK 16'hfffc `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.ecc_int_en_reg // Register template referenced: ecc_mem_reg_grp::ecc_int_en_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__OFFSET 16'h0018 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__RESET_MASK 16'hfffc `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_INT_EN_REG__WRITE_MASK 16'h0003 // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.int_cnt_reg // Register template referenced: ecc_mem_reg_grp::int_cnt_reg `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__INT_CNT_REG__OFFSET 16'h001a `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__INT_CNT_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__INT_CNT_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__INT_CNT_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__INT_CNT_REG__WRITE_MASK 16'hffff // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.ecc_err_addr_reg // Register template referenced: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=12 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__OFFSET 16'h001c `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__RESET_MASK 16'hf000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_ERR_ADDR_REG__WRITE_MASK 16'h0fff // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.diag_cntrl_reg // Register template referenced: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=12:has_diagnostic_read=True `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__OFFSET 16'h001e `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__RESET_MASK 16'h3000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DIAG_CNTRL_REG__WRITE_MASK 16'hcfff // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.ecc_bits_reg // Register template referenced: ecc_mem_reg_grp::ecc_bits_reg:protection_bitwidth=8 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__OFFSET 16'h0020 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__RESET_VALUE 16'h0000 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__RESET_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__ECC_BITS_REG__WRITE_MASK 16'h00ff // Register instance: ecc_mem_reg_grp:address_bitwidth=12:protection_bitwidth=8.data_reg // Register template referenced: ecc_mem_reg_grp::data_reg:data_bitwidth=16 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DATA_REG__OFFSET 16'h0040 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DATA_REG__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DATA_REG__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DATA_REG__READ_MASK 16'hffff `define ECC_MEM_REG_GRP__ADDRESS_BITWIDTH__12__PROTECTION_BITWIDTH__8__DATA_REG__WRITE_MASK 16'hffff // Register template: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=12 // Source filename: ecc.csr, line: 169 // Field instance: ecc_mem_reg_grp::ecc_err_addr_reg:address_bitwidth=12.address `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__MSB 11 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__LSB 0 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__WIDTH 12 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__RANGE 11:0 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__READ_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__ECC_ERR_ADDR_REG__ADDRESS_BITWIDTH__12__ADDRESS__MASK 16'h0fff // Register template: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=12:has_diagnostic_read=True // Source filename: ecc.csr, line: 190 // Field instance: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=12:has_diagnostic_read=True.initiate `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__MSB 15 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__LSB 15 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__WIDTH 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__RANGE 15:15 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__INITIATE__MASK 16'h8000 // Field instance: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=12:has_diagnostic_read=True.read `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__MSB 14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__LSB 14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__WIDTH 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__RANGE 14:14 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__READ__MASK 16'h4000 // Field instance: ecc_mem_reg_grp::diag_cntrl_reg:address_bitwidth=12:has_diagnostic_read=True.diagnostic_address `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__MSB 11 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__LSB 0 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__WIDTH 12 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__RANGE 11:0 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__READ_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__WRITE_ACCESS 1 `define ECC_MEM_REG_GRP__DIAG_CNTRL_REG__ADDRESS_BITWIDTH__12__HAS_DIAGNOSTIC_READ__TRUE__DIAGNOSTIC_ADDRESS__MASK 16'h0fff // Register template: ECC_regs::pkt_memory // Source filename: ecc.csr, line: 322 // Field instance: ECC_regs::pkt_memory.data `define ECC_REGS__PKT_MEMORY__DATA__MSB 15 `define ECC_REGS__PKT_MEMORY__DATA__LSB 0 `define ECC_REGS__PKT_MEMORY__DATA__WIDTH 16 `define ECC_REGS__PKT_MEMORY__DATA__RANGE 15:0 `define ECC_REGS__PKT_MEMORY__DATA__READ_ACCESS 1 `define ECC_REGS__PKT_MEMORY__DATA__WRITE_ACCESS 1 `define ECC_REGS__PKT_MEMORY__DATA__MASK 16'hffff `endif