Address,Position,Title,Identifier,Type,Access,Reset Value,Interrupt Enable,Output port,Description
,,ECC_legacy,ecc_legacy,addressmap,,,,,
0x0,,chip_config,chip_config,register,,,,,
,[0],VPN Passthrough Enable,vpn_passthrough_enable,configuration,R/W,0x0,,,When this bit is asserted VPN packets are forwarded.  When is bit is deasserted VPN packets are blocked.
0x80,,Packet Buffer Memory ECC Control Register,ecc_cntrl_reg,register,,,,,This register provides the control bits for the Packet Buffer Memory.
,[1],Diagnostic Enable,diag_en,configuration,R/W,0x0,,port:,"This bit enables ECC diagnostic mode. When this bit is asserted the write data for the protections bits is provided by the ECC Protection Bits Register.
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,[0],Correct Enable,correct_en,configuration,R/W,0x0,,port:,This bit enables ECC correction.
0x82,,Packet Buffer Memory ECC Interrupt Read-Cl,ecc_int_reg,register,,,,,This register contains the ECC error interrupt bits for the Packet Buffer Memory. The interrupts bits will be cleared on read.
,[1],ECC Single-bit Error Interrupt,sbe_int,interrupt,RC/W,,field:ecc_int_en_reg.sbe_int_en,port:,Set when a single-bit error occurs.
,[0],ECC Multi-bit Error Interrupt,mbe_int,interrupt,RC/W,,field:ecc_int_en_reg.mbe_int_en,port:,Set when a multi-bit error occurs.
0x98,,Packet Buffer Memory ECC Interrupt Enable ,ecc_int_en_reg,register,,,,,This register contains the interrupt enable bits for the Packet Buffer Memory.
,[1],ECC Single-bit Error Interrupt Enable,sbe_int_en,configuration,R/W,,,,Enables single-bit error interrupt
,[0],ECC Multi-bit Error Interrupt Enable,mbe_int_en,configuration,R/W,,,,Enables multi-bit error interrupt
0x9a,,Packet Buffer Memory ECC Error Address Reg,ecc_err_addr_reg,register,,,,,This register contains the address of the read of the Packet Buffer Memory read that had an ECC error.
,[13:0],ECC Error Address,address,configuration,R/W,,,,This field contains the address of the error
0x9c,,Packet Buffer Memory Diagnostic Control Re,diag_cntrl_reg,register,,,,,This register provide the diagnostic control for the Packet Buffer Memory.
,[15],Initiate,initiate,configuration,R/W,,,port:,When this bit is asserted it will initiate a transaction to the memory.  If this register is written with this bit deasserted no transaction will occur.  This bit will clear when the memory transaction is completed.
,[14],Read Command,read,configuration,R/W,,,port:,If this bit is asserted a read occurs when a diagnostic transaction is initiated.
,[13:0],diagnostic_address,diagnostic_address,configuration,R/W,,,,This field contains the address of the error
0x9e,,Packet Buffer Memory ECC Protection Bits R,ecc_bits_reg,register,,,,,This register provides access to the ECC protection bits for the Packet Buffer Memory.
,[7:0],ECC Value,ecc_bits,configuration,R/W,0x00,,port:,This register provides access to the data bits of the Packet Buffer Memory data bits..
0xa0,,Packet Buffer Memory Data Bits Register,data_reg,register,,,,,This field provides the read data bit of the memory after every read operation.  When diagnostic mode is asserted this data is used to write the memory.
,[15:0],Memory data bits,data_value,configuration,R/W,,,,This field provides the read data bit of the memory after every read operation.  When diagnostic mode is asserted this data is used to write the memory.
0x200,,Rx Buffer Memory ECC Control Register,rx_ecc_cntrl_reg,register,,,,,This register provides the control bits for the Rx Buffer Memory.
,[1],Rx Buffer Diagnostic Enable,rx_diag_en,configuration,R/W,0x0,,port:,This bit enables ECC diagnostic mode. When this bit is asserted the write data for the protections bits is provided by the ECC Protection Bits Register.
,[0],Rx Buffer Correct Enable,rx_correct_en,configuration,R/W,0x0,,port:,This bit enables ECC correction.
0x202,,Rx Buffer Memory ECC Interrupt Read-Clear ,rx_ecc_int_reg,register,,,,,This register contains the ECC error interrupt bits for the Rx Buffer Memory. The interrupts bits will be cleared on read.
,[1],Rx Buffer Single-bit Error Interrupt,rx_sbe_int,interrupt,RC/W,,field:rx_ecc_int_en_reg.rx_sbe_int_en,port:,Set when a single-bit error occurs.
,[0],Rx Buffer Multi-bit Error Interrupt,rx_mbe_int,interrupt,RC/W,,field:rx_ecc_int_en_reg.rx_mbe_int_en,port:,Set when a multi-bit error occurs.
0x218,,Rx Buffer Memory ECC Interrupt Enable Regi ,rx_ecc_int_en_reg,register,,,,,This register contains the interrupt enable bits for the Rx Buffer Memory.
,[1],Rx Buffer Single-bit Error Interrupt Enable,rx_sbe_int_en,configuration,R/W,,,,Enables single-bit error interrupt
,[0],Rx Buffer Single-bit Error Interrupt Enable,rx_mbe_int_en,configuration,R/W,,,,Enables multi-bit error interrupt
0x21a,,Rx Buffer Memory ECC Error Address Registe,rx_ecc_err_addr_reg,register,,,,,This register contains the address of the read of the Rx Buffer Memory read that had an ECC error.
,[13:0],Rx Buffer Error Address,rx_address,configuration,R/W,,,,This field contains the address of the error
0x21c,,Rx Buffer Memory Diagnostic Control Regist,rx_diag_cntrl_reg,register,,,,,This register provide the diagnostic control for the Rx Buffer Memory.
,[15],Rx Buffer Initiate,rx_initiate,configuration,R/W,,,port:,When this bit is asserted it will initiate a transaction to the memory.  If this register is written with this bit deasserted no transaction will occur.  This bit will clear when the memory transaction is completed.
,[14],Rx Buffer Read,rx_read,configuration,R/W,,,port:,If this bit is asserted a read occurs when a diagnostic transaction is initiated.
,[13:0],Rx Buffer Diagnostic Address,rx_diagnostic_address,configuration,R/W,,,,This field contains the address of the error
0x21e,,Rx Buffer Memory ECC Protection Bits Regis,rx_ecc_bits_reg,register,,,,,This register provides access to the ECC protection bits for the Rx Buffer Memory.
,[7:0],Rx Buffer ECC Value,rx_ecc_bits,configuration,R/W,0x00,,port:,This register provides access to the data bits of the Rx Buffer Memory data bits..
0x240,,Rx Buffer Memory Data Bits Register,rx_data_reg,register,,,,,This field provides the read data bit of the memory after every read operation.  When diagnostic mode is asserted this data is used to write the memory.
,[15:0],Rx Buffer Memory Data Bits,rx_data_value,configuration,R/W,,,,"This field provides the read data bit of the memory after every read operation.  When diagnostic mode is asserted this data is used to write the memory.
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0x400,,Tx Buffer Memory ECC Control Register,tx_ecc_cntrl_reg,register,,,,,This register provides the control bits for the Rx Buffer Memory.
,[1],Tx Buffer Diagnostic Enable,tx_diag_en,configuration,R/W,0x0,,port:,This bit enables ECC diagnostic mode. When this bit is asserted the write data for the protections bits is provided by the ECC Protection Bits Register.
,[0],Tx Buffer Correct Enable,tx_correct_en,configuration,R/W,0x0,,port:,This bit enables ECC correction.
0x402,,Tx Buffer Memory ECC Interrupt Read-Clear  ,tx_ecc_int_reg,register,,,,,This register contains the ECC error interrupt bits for the Rx Buffer Memory. The interrupts bits will be cleared on read.
,[1],Tx Buffer Single-bit Error Interrupt,tx_sbe_int,interrupt,RC/W,,field:tx_ecc_int_en_reg.tx_sbe_int_en,port:,Set when a single-bit error occurs.
,[0],Tx Buffer Multi-bit Error Interrupt,tx_mbe_int,interrupt,RC/W,,field:tx_ecc_int_en_reg.tx_mbe_int_en,port:,Set when a multi-bit error occurs.
0x418,,Tx Buffer Memory ECC Interrupt Enable Regi ,tx_ecc_int_en_reg,register,,,,,This register contains the interrupt enable bits for the Rx Buffer Memory.
,[1],Tx Buffer Single-bit Error Interrupt Enable,tx_sbe_int_en,configuration,R/W,,,,Enables single-bit error interrupt
,[0],Tx Buffer Single-bit Error Interrupt Enable,tx_mbe_int_en,configuration,R/W,,,,Enables multi-bit error interrupt
0x41a,,Tx Buffer Memory ECC Error Address Registe,tx_ecc_err_addr_reg,register,,,,,This register contains the address of the read of the Rx Buffer Memory read that had an ECC error.
,[13:0],TRx Buffer Error Address,tx_address,configuration,R/W,,,,This field contains the address of the error
0x41c,,Tx Buffer Memory Diagnostic Control Regist,tx_diag_cntrl_reg,register,,,,,This register provide the diagnostic control for the Rx Buffer Memory.
,[15],Tx Buffer Initiate,tx_initiate,configuration,R/W,,,port:,When this bit is asserted it will initiate a transaction to the memory.  If this register is written with this bit deasserted no transaction will occur.  This bit will clear when the memory transaction is completed.
,[14],Tx Buffer Read,tx_read,configuration,R/W,,,port:,If this bit is asserted a read occurs when a diagnostic transaction is initiated.
,[13:0],Tx Buffer Diagnostic Address,tx_diagnostic_address,configuration,R/W,,,,This field contains the address of the error
0x41e,,Tx Buffer Memory ECC Protection Bits Regis,tx_ecc_bits_reg,register,,,,,This register provides access to the ECC protection bits for the Tx Buffer Memory.
,[7:0],Tx Buffer ECC Value,tx_ecc_bits,configuration,R/W,0x00,,port:,This field contains the ECC protection bits. This field contains ECC protection bits form the last read. When the diagnostic mode is 1 then this field is used to write the ECC memory bits instead of the calculated protection bits.
0x440,,Tx Buffer Memory Data Bits Register,tx_data_reg,register,,,,,This field provides the read data bit of the memory after every read operation.  When diagnostic mode is asserted this data is used to write the memory.
,[15:0],Tx Buffer Memory Data Bits,tx_data_value,configuration,R/W,,,port:,This field provides the read data bit of the memory after every read operation.  When diagnostic mode is asserted this data is used to write the memory.