// // Generated by Semifore, Inc. csrCompile // Version: 2008.03 // Released on: Jul 26 2008 09:34:09 // Verilog output // // Input file: ecclegacy.csv // // Generated on: Wed Jul 30 15:36:23 2008 // by: weber // // // Addressmap: ecc_legacy // // Bus Protocol: Basic // Bus combinatorial input and output // // Access: read-write // module ecc_legacy ( csr_read_data, ecc_int_reg_sbe_int_source, ecc_int_reg_mbe_int_source, rx_ecc_int_reg_rx_sbe_int_source, rx_ecc_int_reg_rx_mbe_int_source, tx_ecc_int_reg_tx_sbe_int_source, tx_ecc_int_reg_tx_mbe_int_source, csr_address, csr_read_access, csr_write_access, csr_write_data, reset, clock ); output [15:0] csr_read_data; input ecc_int_reg_sbe_int_source; input ecc_int_reg_mbe_int_source; input rx_ecc_int_reg_rx_sbe_int_source; input rx_ecc_int_reg_rx_mbe_int_source; input tx_ecc_int_reg_tx_sbe_int_source; input tx_ecc_int_reg_tx_mbe_int_source; input [10:0] csr_address; input csr_read_access; input csr_write_access; input [15:0] csr_write_data; input reset; input clock; // output wire declarations wire [15:0] csr_read_data; // input wire declarations wire ecc_int_reg_sbe_int_source; wire ecc_int_reg_mbe_int_source; wire rx_ecc_int_reg_rx_sbe_int_source; wire rx_ecc_int_reg_rx_mbe_int_source; wire tx_ecc_int_reg_tx_sbe_int_source; wire tx_ecc_int_reg_tx_mbe_int_source; wire [10:0] csr_address; wire csr_read_access; wire csr_write_access; wire [15:0] csr_write_data; wire reset; wire clock; // internal net declarations reg csr_internal_field_chip_config_vpn_passthrough_enable; reg csr_internal_field_ecc_cntrl_reg_diag_en; reg csr_internal_field_ecc_cntrl_reg_correct_en; reg csr_internal_field_ecc_int_reg_sbe_int; reg csr_internal_field_ecc_int_reg_mbe_int; reg csr_internal_field_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_ecc_int_en_reg_mbe_int_en; reg [13:0] csr_internal_field_ecc_err_addr_reg_address; reg csr_internal_field_diag_cntrl_reg_initiate; reg csr_internal_field_diag_cntrl_reg_read; reg [13:0] csr_internal_field_diag_cntrl_reg_diagnostic_address; reg [7:0] csr_internal_field_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_data_reg_data_value; reg csr_internal_field_rx_ecc_cntrl_reg_rx_diag_en; reg csr_internal_field_rx_ecc_cntrl_reg_rx_correct_en; reg csr_internal_field_rx_ecc_int_reg_rx_sbe_int; reg csr_internal_field_rx_ecc_int_reg_rx_mbe_int; reg csr_internal_field_rx_ecc_int_en_reg_rx_sbe_int_en; reg csr_internal_field_rx_ecc_int_en_reg_rx_mbe_int_en; reg [13:0] csr_internal_field_rx_ecc_err_addr_reg_rx_address; reg csr_internal_field_rx_diag_cntrl_reg_rx_initiate; reg csr_internal_field_rx_diag_cntrl_reg_rx_read; reg [13:0] csr_internal_field_rx_diag_cntrl_reg_rx_diagnostic_address; reg [7:0] csr_internal_field_rx_ecc_bits_reg_rx_ecc_bits; reg [15:0] csr_internal_field_rx_data_reg_rx_data_value; reg csr_internal_field_tx_ecc_cntrl_reg_tx_diag_en; reg csr_internal_field_tx_ecc_cntrl_reg_tx_correct_en; reg csr_internal_field_tx_ecc_int_reg_tx_sbe_int; reg csr_internal_field_tx_ecc_int_reg_tx_mbe_int; reg csr_internal_field_tx_ecc_int_en_reg_tx_sbe_int_en; reg csr_internal_field_tx_ecc_int_en_reg_tx_mbe_int_en; reg [13:0] csr_internal_field_tx_ecc_err_addr_reg_tx_address; reg csr_internal_field_tx_diag_cntrl_reg_tx_initiate; reg csr_internal_field_tx_diag_cntrl_reg_tx_read; reg [13:0] csr_internal_field_tx_diag_cntrl_reg_tx_diagnostic_address; reg [7:0] csr_internal_field_tx_ecc_bits_reg_tx_ecc_bits; reg [15:0] csr_internal_field_tx_data_reg_tx_data_value; wire csr_internal_next_field_chip_config_vpn_passthrough_enable; wire csr_internal_write_access_chip_config_vpn_passthrough_enable; wire csr_internal_decode_chip_config; wire [15:0] csr_internal_read_data_chip_config; wire csr_internal_next_field_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_ecc_cntrl_reg_correct_en; wire csr_internal_decode_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_ecc_cntrl_reg; wire csr_internal_next_field_ecc_int_reg_sbe_int; wire csr_internal_write_access_ecc_int_reg_sbe_int; wire csr_internal_read_access_ecc_int_reg_sbe_int; wire csr_internal_next_field_ecc_int_reg_mbe_int; wire csr_internal_write_access_ecc_int_reg_mbe_int; wire csr_internal_read_access_ecc_int_reg_mbe_int; wire csr_internal_decode_ecc_int_reg; wire [15:0] csr_internal_read_data_ecc_int_reg; wire csr_internal_next_field_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_ecc_int_en_reg; wire [15:0] csr_internal_read_data_ecc_int_en_reg; wire [13:0] csr_internal_next_field_ecc_err_addr_reg_address; wire csr_internal_write_access_ecc_err_addr_reg_address; wire csr_internal_decode_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_ecc_err_addr_reg; wire csr_internal_next_field_diag_cntrl_reg_initiate; wire csr_internal_write_access_diag_cntrl_reg_initiate; wire csr_internal_next_field_diag_cntrl_reg_read; wire csr_internal_write_access_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_diag_cntrl_reg; wire [15:0] csr_internal_read_data_diag_cntrl_reg; wire [7:0] csr_internal_next_field_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_ecc_bits_reg_ecc_bits; wire csr_internal_decode_ecc_bits_reg; wire [15:0] csr_internal_read_data_ecc_bits_reg; wire [15:0] csr_internal_next_field_data_reg_data_value; wire csr_internal_write_access_data_reg_data_value; wire csr_internal_decode_data_reg; wire [15:0] csr_internal_read_data_data_reg; wire csr_internal_next_field_rx_ecc_cntrl_reg_rx_diag_en; wire csr_internal_write_access_rx_ecc_cntrl_reg_rx_diag_en; wire csr_internal_next_field_rx_ecc_cntrl_reg_rx_correct_en; wire csr_internal_write_access_rx_ecc_cntrl_reg_rx_correct_en; wire csr_internal_decode_rx_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_rx_ecc_cntrl_reg; wire csr_internal_next_field_rx_ecc_int_reg_rx_sbe_int; wire csr_internal_write_access_rx_ecc_int_reg_rx_sbe_int; wire csr_internal_read_access_rx_ecc_int_reg_rx_sbe_int; wire csr_internal_next_field_rx_ecc_int_reg_rx_mbe_int; wire csr_internal_write_access_rx_ecc_int_reg_rx_mbe_int; wire csr_internal_read_access_rx_ecc_int_reg_rx_mbe_int; wire csr_internal_decode_rx_ecc_int_reg; wire [15:0] csr_internal_read_data_rx_ecc_int_reg; wire csr_internal_next_field_rx_ecc_int_en_reg_rx_sbe_int_en; wire csr_internal_write_access_rx_ecc_int_en_reg_rx_sbe_int_en; wire csr_internal_next_field_rx_ecc_int_en_reg_rx_mbe_int_en; wire csr_internal_write_access_rx_ecc_int_en_reg_rx_mbe_int_en; wire csr_internal_decode_rx_ecc_int_en_reg; wire [15:0] csr_internal_read_data_rx_ecc_int_en_reg; wire [13:0] csr_internal_next_field_rx_ecc_err_addr_reg_rx_address; wire csr_internal_write_access_rx_ecc_err_addr_reg_rx_address; wire csr_internal_decode_rx_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_rx_ecc_err_addr_reg; wire csr_internal_next_field_rx_diag_cntrl_reg_rx_initiate; wire csr_internal_write_access_rx_diag_cntrl_reg_rx_initiate; wire csr_internal_next_field_rx_diag_cntrl_reg_rx_read; wire csr_internal_write_access_rx_diag_cntrl_reg_rx_read; wire [13:0] csr_internal_next_field_rx_diag_cntrl_reg_rx_diagnostic_address; wire csr_internal_write_access_rx_diag_cntrl_reg_rx_diagnostic_address; wire csr_internal_decode_rx_diag_cntrl_reg; wire [15:0] csr_internal_read_data_rx_diag_cntrl_reg; wire [7:0] csr_internal_next_field_rx_ecc_bits_reg_rx_ecc_bits; wire csr_internal_write_access_rx_ecc_bits_reg_rx_ecc_bits; wire csr_internal_decode_rx_ecc_bits_reg; wire [15:0] csr_internal_read_data_rx_ecc_bits_reg; wire [15:0] csr_internal_next_field_rx_data_reg_rx_data_value; wire csr_internal_write_access_rx_data_reg_rx_data_value; wire csr_internal_decode_rx_data_reg; wire [15:0] csr_internal_read_data_rx_data_reg; wire csr_internal_next_field_tx_ecc_cntrl_reg_tx_diag_en; wire csr_internal_write_access_tx_ecc_cntrl_reg_tx_diag_en; wire csr_internal_next_field_tx_ecc_cntrl_reg_tx_correct_en; wire csr_internal_write_access_tx_ecc_cntrl_reg_tx_correct_en; wire csr_internal_decode_tx_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_tx_ecc_cntrl_reg; wire csr_internal_next_field_tx_ecc_int_reg_tx_sbe_int; wire csr_internal_write_access_tx_ecc_int_reg_tx_sbe_int; wire csr_internal_read_access_tx_ecc_int_reg_tx_sbe_int; wire csr_internal_next_field_tx_ecc_int_reg_tx_mbe_int; wire csr_internal_write_access_tx_ecc_int_reg_tx_mbe_int; wire csr_internal_read_access_tx_ecc_int_reg_tx_mbe_int; wire csr_internal_decode_tx_ecc_int_reg; wire [15:0] csr_internal_read_data_tx_ecc_int_reg; wire csr_internal_next_field_tx_ecc_int_en_reg_tx_sbe_int_en; wire csr_internal_write_access_tx_ecc_int_en_reg_tx_sbe_int_en; wire csr_internal_next_field_tx_ecc_int_en_reg_tx_mbe_int_en; wire csr_internal_write_access_tx_ecc_int_en_reg_tx_mbe_int_en; wire csr_internal_decode_tx_ecc_int_en_reg; wire [15:0] csr_internal_read_data_tx_ecc_int_en_reg; wire [13:0] csr_internal_next_field_tx_ecc_err_addr_reg_tx_address; wire csr_internal_write_access_tx_ecc_err_addr_reg_tx_address; wire csr_internal_decode_tx_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_tx_ecc_err_addr_reg; wire csr_internal_next_field_tx_diag_cntrl_reg_tx_initiate; wire csr_internal_write_access_tx_diag_cntrl_reg_tx_initiate; wire csr_internal_next_field_tx_diag_cntrl_reg_tx_read; wire csr_internal_write_access_tx_diag_cntrl_reg_tx_read; wire [13:0] csr_internal_next_field_tx_diag_cntrl_reg_tx_diagnostic_address; wire csr_internal_write_access_tx_diag_cntrl_reg_tx_diagnostic_address; wire csr_internal_decode_tx_diag_cntrl_reg; wire [15:0] csr_internal_read_data_tx_diag_cntrl_reg; wire [7:0] csr_internal_next_field_tx_ecc_bits_reg_tx_ecc_bits; wire csr_internal_write_access_tx_ecc_bits_reg_tx_ecc_bits; wire csr_internal_decode_tx_ecc_bits_reg; wire [15:0] csr_internal_read_data_tx_ecc_bits_reg; wire [15:0] csr_internal_next_field_tx_data_reg_tx_data_value; wire csr_internal_write_access_tx_data_reg_tx_data_value; wire csr_internal_decode_tx_data_reg; wire [15:0] csr_internal_read_data_tx_data_reg; wire [10:0] csr_internal_bus_address; wire csr_internal_bus_read_access; wire [15:0] csr_internal_read_data; wire [15:0] csr_internal_bus_read_data; wire csr_internal_read_access; wire csr_internal_bus_write_access; wire [15:0] csr_internal_bus_write_data; wire csr_internal_write_access; // Bus Protocol: Basic // Bus combinatorial input and output assign csr_internal_bus_address = csr_address; assign csr_internal_bus_write_access = csr_write_access; assign csr_internal_bus_write_data = csr_write_data; assign csr_internal_bus_read_access = csr_read_access; assign csr_read_data = csr_internal_bus_read_data; assign csr_internal_read_access = csr_internal_bus_read_access; assign csr_internal_bus_read_data = (csr_internal_read_access) ? csr_internal_read_data: 16'b0; assign csr_internal_write_access = csr_internal_bus_write_access; // Address Decode assign csr_internal_decode_chip_config = (csr_internal_bus_address[10:1] == 10'h0); assign csr_internal_decode_ecc_cntrl_reg = (csr_internal_bus_address[10:1] == 10'h40); assign csr_internal_decode_ecc_int_reg = (csr_internal_bus_address[10:1] == 10'h41); assign csr_internal_decode_ecc_int_en_reg = (csr_internal_bus_address[10:1] == 10'h4c); assign csr_internal_decode_ecc_err_addr_reg = (csr_internal_bus_address[10:1] == 10'h4d); assign csr_internal_decode_diag_cntrl_reg = (csr_internal_bus_address[10:1] == 10'h4e); assign csr_internal_decode_ecc_bits_reg = (csr_internal_bus_address[10:1] == 10'h4f); assign csr_internal_decode_data_reg = (csr_internal_bus_address[10:1] == 10'h50); assign csr_internal_decode_rx_ecc_cntrl_reg = (csr_internal_bus_address[10:1] == 10'h100); assign csr_internal_decode_rx_ecc_int_reg = (csr_internal_bus_address[10:1] == 10'h101); assign csr_internal_decode_rx_ecc_int_en_reg = (csr_internal_bus_address[10:1] == 10'h10c); assign csr_internal_decode_rx_ecc_err_addr_reg = (csr_internal_bus_address[10:1] == 10'h10d); assign csr_internal_decode_rx_diag_cntrl_reg = (csr_internal_bus_address[10:1] == 10'h10e); assign csr_internal_decode_rx_ecc_bits_reg = (csr_internal_bus_address[10:1] == 10'h10f); assign csr_internal_decode_rx_data_reg = (csr_internal_bus_address[10:1] == 10'h120); assign csr_internal_decode_tx_ecc_cntrl_reg = (csr_internal_bus_address[10:1] == 10'h200); assign csr_internal_decode_tx_ecc_int_reg = (csr_internal_bus_address[10:1] == 10'h201); assign csr_internal_decode_tx_ecc_int_en_reg = (csr_internal_bus_address[10:1] == 10'h20c); assign csr_internal_decode_tx_ecc_err_addr_reg = (csr_internal_bus_address[10:1] == 10'h20d); assign csr_internal_decode_tx_diag_cntrl_reg = (csr_internal_bus_address[10:1] == 10'h20e); assign csr_internal_decode_tx_ecc_bits_reg = (csr_internal_bus_address[10:1] == 10'h20f); assign csr_internal_decode_tx_data_reg = (csr_internal_bus_address[10:1] == 10'h220); // // Register: chip_config // Addressmap Offset: 0x0 // Access: read-write // assign csr_internal_read_data_chip_config = { 15'h0, csr_internal_field_chip_config_vpn_passthrough_enable } & {16{csr_internal_decode_chip_config}}; // Field: chip_config.vpn_passthrough_enable // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_chip_config_vpn_passthrough_enable = csr_internal_decode_chip_config & csr_internal_write_access; assign csr_internal_next_field_chip_config_vpn_passthrough_enable = (csr_internal_write_access_chip_config_vpn_passthrough_enable) ? csr_internal_bus_write_data[0]: csr_internal_field_chip_config_vpn_passthrough_enable; always @(posedge clock) if (reset) csr_internal_field_chip_config_vpn_passthrough_enable <= 1'h0; else csr_internal_field_chip_config_vpn_passthrough_enable <= csr_internal_next_field_chip_config_vpn_passthrough_enable; // // Register: ecc_cntrl_reg // Addressmap Offset: 0x80 // Access: read-write // assign csr_internal_read_data_ecc_cntrl_reg = { 14'h0, csr_internal_field_ecc_cntrl_reg_diag_en, csr_internal_field_ecc_cntrl_reg_correct_en } & {16{csr_internal_decode_ecc_cntrl_reg}}; // Field: ecc_cntrl_reg.diag_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_ecc_cntrl_reg_diag_en = csr_internal_decode_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_cntrl_reg_diag_en = (csr_internal_write_access_ecc_cntrl_reg_diag_en) ? csr_internal_bus_write_data[1]: csr_internal_field_ecc_cntrl_reg_diag_en; always @(posedge clock) if (reset) csr_internal_field_ecc_cntrl_reg_diag_en <= 1'h0; else csr_internal_field_ecc_cntrl_reg_diag_en <= csr_internal_next_field_ecc_cntrl_reg_diag_en; // Field: ecc_cntrl_reg.correct_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_ecc_cntrl_reg_correct_en = csr_internal_decode_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_cntrl_reg_correct_en = (csr_internal_write_access_ecc_cntrl_reg_correct_en) ? csr_internal_bus_write_data[0]: csr_internal_field_ecc_cntrl_reg_correct_en; always @(posedge clock) if (reset) csr_internal_field_ecc_cntrl_reg_correct_en <= 1'h0; else csr_internal_field_ecc_cntrl_reg_correct_en <= csr_internal_next_field_ecc_cntrl_reg_correct_en; // // Register: ecc_int_reg // Addressmap Offset: 0x82 // Access: read-write // assign csr_internal_read_data_ecc_int_reg = { 14'h0, csr_internal_field_ecc_int_reg_sbe_int, csr_internal_field_ecc_int_reg_mbe_int } & {16{csr_internal_decode_ecc_int_reg}}; // Field: ecc_int_reg.sbe_int // Position: [1] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_ecc_int_reg_sbe_int = csr_internal_decode_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_ecc_int_reg_sbe_int = csr_internal_decode_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_int_reg_sbe_int = (csr_internal_write_access_ecc_int_reg_sbe_int) ? csr_internal_bus_write_data[1]: (ecc_int_reg_sbe_int_source) ? 1'b1: (csr_internal_read_access_ecc_int_reg_sbe_int) ? 1'b0: csr_internal_field_ecc_int_reg_sbe_int; always @(posedge clock) csr_internal_field_ecc_int_reg_sbe_int <= csr_internal_next_field_ecc_int_reg_sbe_int; // Field: ecc_int_reg.mbe_int // Position: [0] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_ecc_int_reg_mbe_int = csr_internal_decode_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_ecc_int_reg_mbe_int = csr_internal_decode_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_int_reg_mbe_int = (csr_internal_write_access_ecc_int_reg_mbe_int) ? csr_internal_bus_write_data[0]: (ecc_int_reg_mbe_int_source) ? 1'b1: (csr_internal_read_access_ecc_int_reg_mbe_int) ? 1'b0: csr_internal_field_ecc_int_reg_mbe_int; always @(posedge clock) csr_internal_field_ecc_int_reg_mbe_int <= csr_internal_next_field_ecc_int_reg_mbe_int; // // Register: ecc_int_en_reg // Addressmap Offset: 0x98 // Access: read-write // assign csr_internal_read_data_ecc_int_en_reg = { 14'h0, csr_internal_field_ecc_int_en_reg_sbe_int_en, csr_internal_field_ecc_int_en_reg_mbe_int_en } & {16{csr_internal_decode_ecc_int_en_reg}}; // Field: ecc_int_en_reg.sbe_int_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_ecc_int_en_reg_sbe_int_en = csr_internal_decode_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_int_en_reg_sbe_int_en = (csr_internal_write_access_ecc_int_en_reg_sbe_int_en) ? csr_internal_bus_write_data[1]: csr_internal_field_ecc_int_en_reg_sbe_int_en; always @(posedge clock) csr_internal_field_ecc_int_en_reg_sbe_int_en <= csr_internal_next_field_ecc_int_en_reg_sbe_int_en; // Field: ecc_int_en_reg.mbe_int_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_ecc_int_en_reg_mbe_int_en = csr_internal_decode_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_int_en_reg_mbe_int_en = (csr_internal_write_access_ecc_int_en_reg_mbe_int_en) ? csr_internal_bus_write_data[0]: csr_internal_field_ecc_int_en_reg_mbe_int_en; always @(posedge clock) csr_internal_field_ecc_int_en_reg_mbe_int_en <= csr_internal_next_field_ecc_int_en_reg_mbe_int_en; // // Register: ecc_err_addr_reg // Addressmap Offset: 0x9a // Access: read-write // assign csr_internal_read_data_ecc_err_addr_reg = { 2'h0, csr_internal_field_ecc_err_addr_reg_address } & {16{csr_internal_decode_ecc_err_addr_reg}}; // Field: ecc_err_addr_reg.address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_ecc_err_addr_reg_address = csr_internal_decode_ecc_err_addr_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_err_addr_reg_address = (csr_internal_write_access_ecc_err_addr_reg_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_ecc_err_addr_reg_address; always @(posedge clock) csr_internal_field_ecc_err_addr_reg_address <= csr_internal_next_field_ecc_err_addr_reg_address; // // Register: diag_cntrl_reg // Addressmap Offset: 0x9c // Access: read-write // assign csr_internal_read_data_diag_cntrl_reg = { csr_internal_field_diag_cntrl_reg_initiate, csr_internal_field_diag_cntrl_reg_read, csr_internal_field_diag_cntrl_reg_diagnostic_address } & {16{csr_internal_decode_diag_cntrl_reg}}; // Field: diag_cntrl_reg.initiate // Position: [15] // Access: read-write // Type: configuration assign csr_internal_write_access_diag_cntrl_reg_initiate = csr_internal_decode_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_diag_cntrl_reg_initiate = (csr_internal_write_access_diag_cntrl_reg_initiate) ? csr_internal_bus_write_data[15]: csr_internal_field_diag_cntrl_reg_initiate; always @(posedge clock) csr_internal_field_diag_cntrl_reg_initiate <= csr_internal_next_field_diag_cntrl_reg_initiate; // Field: diag_cntrl_reg.read // Position: [14] // Access: read-write // Type: configuration assign csr_internal_write_access_diag_cntrl_reg_read = csr_internal_decode_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_diag_cntrl_reg_read = (csr_internal_write_access_diag_cntrl_reg_read) ? csr_internal_bus_write_data[14]: csr_internal_field_diag_cntrl_reg_read; always @(posedge clock) csr_internal_field_diag_cntrl_reg_read <= csr_internal_next_field_diag_cntrl_reg_read; // Field: diag_cntrl_reg.diagnostic_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_diag_cntrl_reg_diagnostic_address = csr_internal_decode_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_diag_cntrl_reg_diagnostic_address = (csr_internal_write_access_diag_cntrl_reg_diagnostic_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_diag_cntrl_reg_diagnostic_address; always @(posedge clock) csr_internal_field_diag_cntrl_reg_diagnostic_address <= csr_internal_next_field_diag_cntrl_reg_diagnostic_address; // // Register: ecc_bits_reg // Addressmap Offset: 0x9e // Access: read-write // assign csr_internal_read_data_ecc_bits_reg = { 8'h0, csr_internal_field_ecc_bits_reg_ecc_bits } & {16{csr_internal_decode_ecc_bits_reg}}; // Field: ecc_bits_reg.ecc_bits // Position: [7:0] // Access: read-write // Type: configuration assign csr_internal_write_access_ecc_bits_reg_ecc_bits = csr_internal_decode_ecc_bits_reg & csr_internal_write_access; assign csr_internal_next_field_ecc_bits_reg_ecc_bits = (csr_internal_write_access_ecc_bits_reg_ecc_bits) ? csr_internal_bus_write_data[7:0]: csr_internal_field_ecc_bits_reg_ecc_bits; always @(posedge clock) if (reset) csr_internal_field_ecc_bits_reg_ecc_bits <= 8'h0; else csr_internal_field_ecc_bits_reg_ecc_bits <= csr_internal_next_field_ecc_bits_reg_ecc_bits; // // Register: data_reg // Addressmap Offset: 0xa0 // Access: read-write // assign csr_internal_read_data_data_reg = csr_internal_field_data_reg_data_value & {16{csr_internal_decode_data_reg}}; // Field: data_reg.data_value // Position: [15:0] // Access: read-write // Type: configuration assign csr_internal_write_access_data_reg_data_value = csr_internal_decode_data_reg & csr_internal_write_access; assign csr_internal_next_field_data_reg_data_value = (csr_internal_write_access_data_reg_data_value) ? csr_internal_bus_write_data: csr_internal_field_data_reg_data_value; always @(posedge clock) csr_internal_field_data_reg_data_value <= csr_internal_next_field_data_reg_data_value; // // Register: rx_ecc_cntrl_reg // Addressmap Offset: 0x200 // Access: read-write // assign csr_internal_read_data_rx_ecc_cntrl_reg = { 14'h0, csr_internal_field_rx_ecc_cntrl_reg_rx_diag_en, csr_internal_field_rx_ecc_cntrl_reg_rx_correct_en } & {16{csr_internal_decode_rx_ecc_cntrl_reg}}; // Field: rx_ecc_cntrl_reg.rx_diag_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_ecc_cntrl_reg_rx_diag_en = csr_internal_decode_rx_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_cntrl_reg_rx_diag_en = (csr_internal_write_access_rx_ecc_cntrl_reg_rx_diag_en) ? csr_internal_bus_write_data[1]: csr_internal_field_rx_ecc_cntrl_reg_rx_diag_en; always @(posedge clock) if (reset) csr_internal_field_rx_ecc_cntrl_reg_rx_diag_en <= 1'h0; else csr_internal_field_rx_ecc_cntrl_reg_rx_diag_en <= csr_internal_next_field_rx_ecc_cntrl_reg_rx_diag_en; // Field: rx_ecc_cntrl_reg.rx_correct_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_ecc_cntrl_reg_rx_correct_en = csr_internal_decode_rx_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_cntrl_reg_rx_correct_en = (csr_internal_write_access_rx_ecc_cntrl_reg_rx_correct_en) ? csr_internal_bus_write_data[0]: csr_internal_field_rx_ecc_cntrl_reg_rx_correct_en; always @(posedge clock) if (reset) csr_internal_field_rx_ecc_cntrl_reg_rx_correct_en <= 1'h0; else csr_internal_field_rx_ecc_cntrl_reg_rx_correct_en <= csr_internal_next_field_rx_ecc_cntrl_reg_rx_correct_en; // // Register: rx_ecc_int_reg // Addressmap Offset: 0x202 // Access: read-write // assign csr_internal_read_data_rx_ecc_int_reg = { 14'h0, csr_internal_field_rx_ecc_int_reg_rx_sbe_int, csr_internal_field_rx_ecc_int_reg_rx_mbe_int } & {16{csr_internal_decode_rx_ecc_int_reg}}; // Field: rx_ecc_int_reg.rx_sbe_int // Position: [1] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_rx_ecc_int_reg_rx_sbe_int = csr_internal_decode_rx_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_rx_ecc_int_reg_rx_sbe_int = csr_internal_decode_rx_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_int_reg_rx_sbe_int = (csr_internal_write_access_rx_ecc_int_reg_rx_sbe_int) ? csr_internal_bus_write_data[1]: (rx_ecc_int_reg_rx_sbe_int_source) ? 1'b1: (csr_internal_read_access_rx_ecc_int_reg_rx_sbe_int) ? 1'b0: csr_internal_field_rx_ecc_int_reg_rx_sbe_int; always @(posedge clock) csr_internal_field_rx_ecc_int_reg_rx_sbe_int <= csr_internal_next_field_rx_ecc_int_reg_rx_sbe_int; // Field: rx_ecc_int_reg.rx_mbe_int // Position: [0] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_rx_ecc_int_reg_rx_mbe_int = csr_internal_decode_rx_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_rx_ecc_int_reg_rx_mbe_int = csr_internal_decode_rx_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_int_reg_rx_mbe_int = (csr_internal_write_access_rx_ecc_int_reg_rx_mbe_int) ? csr_internal_bus_write_data[0]: (rx_ecc_int_reg_rx_mbe_int_source) ? 1'b1: (csr_internal_read_access_rx_ecc_int_reg_rx_mbe_int) ? 1'b0: csr_internal_field_rx_ecc_int_reg_rx_mbe_int; always @(posedge clock) csr_internal_field_rx_ecc_int_reg_rx_mbe_int <= csr_internal_next_field_rx_ecc_int_reg_rx_mbe_int; // // Register: rx_ecc_int_en_reg // Addressmap Offset: 0x218 // Access: read-write // assign csr_internal_read_data_rx_ecc_int_en_reg = { 14'h0, csr_internal_field_rx_ecc_int_en_reg_rx_sbe_int_en, csr_internal_field_rx_ecc_int_en_reg_rx_mbe_int_en } & {16{csr_internal_decode_rx_ecc_int_en_reg}}; // Field: rx_ecc_int_en_reg.rx_sbe_int_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_ecc_int_en_reg_rx_sbe_int_en = csr_internal_decode_rx_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_int_en_reg_rx_sbe_int_en = (csr_internal_write_access_rx_ecc_int_en_reg_rx_sbe_int_en) ? csr_internal_bus_write_data[1]: csr_internal_field_rx_ecc_int_en_reg_rx_sbe_int_en; always @(posedge clock) csr_internal_field_rx_ecc_int_en_reg_rx_sbe_int_en <= csr_internal_next_field_rx_ecc_int_en_reg_rx_sbe_int_en; // Field: rx_ecc_int_en_reg.rx_mbe_int_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_ecc_int_en_reg_rx_mbe_int_en = csr_internal_decode_rx_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_int_en_reg_rx_mbe_int_en = (csr_internal_write_access_rx_ecc_int_en_reg_rx_mbe_int_en) ? csr_internal_bus_write_data[0]: csr_internal_field_rx_ecc_int_en_reg_rx_mbe_int_en; always @(posedge clock) csr_internal_field_rx_ecc_int_en_reg_rx_mbe_int_en <= csr_internal_next_field_rx_ecc_int_en_reg_rx_mbe_int_en; // // Register: rx_ecc_err_addr_reg // Addressmap Offset: 0x21a // Access: read-write // assign csr_internal_read_data_rx_ecc_err_addr_reg = { 2'h0, csr_internal_field_rx_ecc_err_addr_reg_rx_address } & {16{csr_internal_decode_rx_ecc_err_addr_reg}}; // Field: rx_ecc_err_addr_reg.rx_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_ecc_err_addr_reg_rx_address = csr_internal_decode_rx_ecc_err_addr_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_err_addr_reg_rx_address = (csr_internal_write_access_rx_ecc_err_addr_reg_rx_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_rx_ecc_err_addr_reg_rx_address; always @(posedge clock) csr_internal_field_rx_ecc_err_addr_reg_rx_address <= csr_internal_next_field_rx_ecc_err_addr_reg_rx_address; // // Register: rx_diag_cntrl_reg // Addressmap Offset: 0x21c // Access: read-write // assign csr_internal_read_data_rx_diag_cntrl_reg = { csr_internal_field_rx_diag_cntrl_reg_rx_initiate, csr_internal_field_rx_diag_cntrl_reg_rx_read, csr_internal_field_rx_diag_cntrl_reg_rx_diagnostic_address } & {16{csr_internal_decode_rx_diag_cntrl_reg}}; // Field: rx_diag_cntrl_reg.rx_initiate // Position: [15] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_diag_cntrl_reg_rx_initiate = csr_internal_decode_rx_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_diag_cntrl_reg_rx_initiate = (csr_internal_write_access_rx_diag_cntrl_reg_rx_initiate) ? csr_internal_bus_write_data[15]: csr_internal_field_rx_diag_cntrl_reg_rx_initiate; always @(posedge clock) csr_internal_field_rx_diag_cntrl_reg_rx_initiate <= csr_internal_next_field_rx_diag_cntrl_reg_rx_initiate; // Field: rx_diag_cntrl_reg.rx_read // Position: [14] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_diag_cntrl_reg_rx_read = csr_internal_decode_rx_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_diag_cntrl_reg_rx_read = (csr_internal_write_access_rx_diag_cntrl_reg_rx_read) ? csr_internal_bus_write_data[14]: csr_internal_field_rx_diag_cntrl_reg_rx_read; always @(posedge clock) csr_internal_field_rx_diag_cntrl_reg_rx_read <= csr_internal_next_field_rx_diag_cntrl_reg_rx_read; // Field: rx_diag_cntrl_reg.rx_diagnostic_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_diag_cntrl_reg_rx_diagnostic_address = csr_internal_decode_rx_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_diag_cntrl_reg_rx_diagnostic_address = (csr_internal_write_access_rx_diag_cntrl_reg_rx_diagnostic_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_rx_diag_cntrl_reg_rx_diagnostic_address; always @(posedge clock) csr_internal_field_rx_diag_cntrl_reg_rx_diagnostic_address <= csr_internal_next_field_rx_diag_cntrl_reg_rx_diagnostic_address; // // Register: rx_ecc_bits_reg // Addressmap Offset: 0x21e // Access: read-write // assign csr_internal_read_data_rx_ecc_bits_reg = { 8'h0, csr_internal_field_rx_ecc_bits_reg_rx_ecc_bits } & {16{csr_internal_decode_rx_ecc_bits_reg}}; // Field: rx_ecc_bits_reg.rx_ecc_bits // Position: [7:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_ecc_bits_reg_rx_ecc_bits = csr_internal_decode_rx_ecc_bits_reg & csr_internal_write_access; assign csr_internal_next_field_rx_ecc_bits_reg_rx_ecc_bits = (csr_internal_write_access_rx_ecc_bits_reg_rx_ecc_bits) ? csr_internal_bus_write_data[7:0]: csr_internal_field_rx_ecc_bits_reg_rx_ecc_bits; always @(posedge clock) if (reset) csr_internal_field_rx_ecc_bits_reg_rx_ecc_bits <= 8'h0; else csr_internal_field_rx_ecc_bits_reg_rx_ecc_bits <= csr_internal_next_field_rx_ecc_bits_reg_rx_ecc_bits; // // Register: rx_data_reg // Addressmap Offset: 0x240 // Access: read-write // assign csr_internal_read_data_rx_data_reg = csr_internal_field_rx_data_reg_rx_data_value & {16{csr_internal_decode_rx_data_reg}}; // Field: rx_data_reg.rx_data_value // Position: [15:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_data_reg_rx_data_value = csr_internal_decode_rx_data_reg & csr_internal_write_access; assign csr_internal_next_field_rx_data_reg_rx_data_value = (csr_internal_write_access_rx_data_reg_rx_data_value) ? csr_internal_bus_write_data: csr_internal_field_rx_data_reg_rx_data_value; always @(posedge clock) csr_internal_field_rx_data_reg_rx_data_value <= csr_internal_next_field_rx_data_reg_rx_data_value; // // Register: tx_ecc_cntrl_reg // Addressmap Offset: 0x400 // Access: read-write // assign csr_internal_read_data_tx_ecc_cntrl_reg = { 14'h0, csr_internal_field_tx_ecc_cntrl_reg_tx_diag_en, csr_internal_field_tx_ecc_cntrl_reg_tx_correct_en } & {16{csr_internal_decode_tx_ecc_cntrl_reg}}; // Field: tx_ecc_cntrl_reg.tx_diag_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_ecc_cntrl_reg_tx_diag_en = csr_internal_decode_tx_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_cntrl_reg_tx_diag_en = (csr_internal_write_access_tx_ecc_cntrl_reg_tx_diag_en) ? csr_internal_bus_write_data[1]: csr_internal_field_tx_ecc_cntrl_reg_tx_diag_en; always @(posedge clock) if (reset) csr_internal_field_tx_ecc_cntrl_reg_tx_diag_en <= 1'h0; else csr_internal_field_tx_ecc_cntrl_reg_tx_diag_en <= csr_internal_next_field_tx_ecc_cntrl_reg_tx_diag_en; // Field: tx_ecc_cntrl_reg.tx_correct_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_ecc_cntrl_reg_tx_correct_en = csr_internal_decode_tx_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_cntrl_reg_tx_correct_en = (csr_internal_write_access_tx_ecc_cntrl_reg_tx_correct_en) ? csr_internal_bus_write_data[0]: csr_internal_field_tx_ecc_cntrl_reg_tx_correct_en; always @(posedge clock) if (reset) csr_internal_field_tx_ecc_cntrl_reg_tx_correct_en <= 1'h0; else csr_internal_field_tx_ecc_cntrl_reg_tx_correct_en <= csr_internal_next_field_tx_ecc_cntrl_reg_tx_correct_en; // // Register: tx_ecc_int_reg // Addressmap Offset: 0x402 // Access: read-write // assign csr_internal_read_data_tx_ecc_int_reg = { 14'h0, csr_internal_field_tx_ecc_int_reg_tx_sbe_int, csr_internal_field_tx_ecc_int_reg_tx_mbe_int } & {16{csr_internal_decode_tx_ecc_int_reg}}; // Field: tx_ecc_int_reg.tx_sbe_int // Position: [1] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_tx_ecc_int_reg_tx_sbe_int = csr_internal_decode_tx_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_tx_ecc_int_reg_tx_sbe_int = csr_internal_decode_tx_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_int_reg_tx_sbe_int = (csr_internal_write_access_tx_ecc_int_reg_tx_sbe_int) ? csr_internal_bus_write_data[1]: (tx_ecc_int_reg_tx_sbe_int_source) ? 1'b1: (csr_internal_read_access_tx_ecc_int_reg_tx_sbe_int) ? 1'b0: csr_internal_field_tx_ecc_int_reg_tx_sbe_int; always @(posedge clock) csr_internal_field_tx_ecc_int_reg_tx_sbe_int <= csr_internal_next_field_tx_ecc_int_reg_tx_sbe_int; // Field: tx_ecc_int_reg.tx_mbe_int // Position: [0] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_tx_ecc_int_reg_tx_mbe_int = csr_internal_decode_tx_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_tx_ecc_int_reg_tx_mbe_int = csr_internal_decode_tx_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_int_reg_tx_mbe_int = (csr_internal_write_access_tx_ecc_int_reg_tx_mbe_int) ? csr_internal_bus_write_data[0]: (tx_ecc_int_reg_tx_mbe_int_source) ? 1'b1: (csr_internal_read_access_tx_ecc_int_reg_tx_mbe_int) ? 1'b0: csr_internal_field_tx_ecc_int_reg_tx_mbe_int; always @(posedge clock) csr_internal_field_tx_ecc_int_reg_tx_mbe_int <= csr_internal_next_field_tx_ecc_int_reg_tx_mbe_int; // // Register: tx_ecc_int_en_reg // Addressmap Offset: 0x418 // Access: read-write // assign csr_internal_read_data_tx_ecc_int_en_reg = { 14'h0, csr_internal_field_tx_ecc_int_en_reg_tx_sbe_int_en, csr_internal_field_tx_ecc_int_en_reg_tx_mbe_int_en } & {16{csr_internal_decode_tx_ecc_int_en_reg}}; // Field: tx_ecc_int_en_reg.tx_sbe_int_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_ecc_int_en_reg_tx_sbe_int_en = csr_internal_decode_tx_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_int_en_reg_tx_sbe_int_en = (csr_internal_write_access_tx_ecc_int_en_reg_tx_sbe_int_en) ? csr_internal_bus_write_data[1]: csr_internal_field_tx_ecc_int_en_reg_tx_sbe_int_en; always @(posedge clock) csr_internal_field_tx_ecc_int_en_reg_tx_sbe_int_en <= csr_internal_next_field_tx_ecc_int_en_reg_tx_sbe_int_en; // Field: tx_ecc_int_en_reg.tx_mbe_int_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_ecc_int_en_reg_tx_mbe_int_en = csr_internal_decode_tx_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_int_en_reg_tx_mbe_int_en = (csr_internal_write_access_tx_ecc_int_en_reg_tx_mbe_int_en) ? csr_internal_bus_write_data[0]: csr_internal_field_tx_ecc_int_en_reg_tx_mbe_int_en; always @(posedge clock) csr_internal_field_tx_ecc_int_en_reg_tx_mbe_int_en <= csr_internal_next_field_tx_ecc_int_en_reg_tx_mbe_int_en; // // Register: tx_ecc_err_addr_reg // Addressmap Offset: 0x41a // Access: read-write // assign csr_internal_read_data_tx_ecc_err_addr_reg = { 2'h0, csr_internal_field_tx_ecc_err_addr_reg_tx_address } & {16{csr_internal_decode_tx_ecc_err_addr_reg}}; // Field: tx_ecc_err_addr_reg.tx_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_ecc_err_addr_reg_tx_address = csr_internal_decode_tx_ecc_err_addr_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_err_addr_reg_tx_address = (csr_internal_write_access_tx_ecc_err_addr_reg_tx_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_tx_ecc_err_addr_reg_tx_address; always @(posedge clock) csr_internal_field_tx_ecc_err_addr_reg_tx_address <= csr_internal_next_field_tx_ecc_err_addr_reg_tx_address; // // Register: tx_diag_cntrl_reg // Addressmap Offset: 0x41c // Access: read-write // assign csr_internal_read_data_tx_diag_cntrl_reg = { csr_internal_field_tx_diag_cntrl_reg_tx_initiate, csr_internal_field_tx_diag_cntrl_reg_tx_read, csr_internal_field_tx_diag_cntrl_reg_tx_diagnostic_address } & {16{csr_internal_decode_tx_diag_cntrl_reg}}; // Field: tx_diag_cntrl_reg.tx_initiate // Position: [15] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_diag_cntrl_reg_tx_initiate = csr_internal_decode_tx_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_tx_diag_cntrl_reg_tx_initiate = (csr_internal_write_access_tx_diag_cntrl_reg_tx_initiate) ? csr_internal_bus_write_data[15]: csr_internal_field_tx_diag_cntrl_reg_tx_initiate; always @(posedge clock) csr_internal_field_tx_diag_cntrl_reg_tx_initiate <= csr_internal_next_field_tx_diag_cntrl_reg_tx_initiate; // Field: tx_diag_cntrl_reg.tx_read // Position: [14] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_diag_cntrl_reg_tx_read = csr_internal_decode_tx_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_tx_diag_cntrl_reg_tx_read = (csr_internal_write_access_tx_diag_cntrl_reg_tx_read) ? csr_internal_bus_write_data[14]: csr_internal_field_tx_diag_cntrl_reg_tx_read; always @(posedge clock) csr_internal_field_tx_diag_cntrl_reg_tx_read <= csr_internal_next_field_tx_diag_cntrl_reg_tx_read; // Field: tx_diag_cntrl_reg.tx_diagnostic_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_diag_cntrl_reg_tx_diagnostic_address = csr_internal_decode_tx_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_tx_diag_cntrl_reg_tx_diagnostic_address = (csr_internal_write_access_tx_diag_cntrl_reg_tx_diagnostic_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_tx_diag_cntrl_reg_tx_diagnostic_address; always @(posedge clock) csr_internal_field_tx_diag_cntrl_reg_tx_diagnostic_address <= csr_internal_next_field_tx_diag_cntrl_reg_tx_diagnostic_address; // // Register: tx_ecc_bits_reg // Addressmap Offset: 0x41e // Access: read-write // assign csr_internal_read_data_tx_ecc_bits_reg = { 8'h0, csr_internal_field_tx_ecc_bits_reg_tx_ecc_bits } & {16{csr_internal_decode_tx_ecc_bits_reg}}; // Field: tx_ecc_bits_reg.tx_ecc_bits // Position: [7:0] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_ecc_bits_reg_tx_ecc_bits = csr_internal_decode_tx_ecc_bits_reg & csr_internal_write_access; assign csr_internal_next_field_tx_ecc_bits_reg_tx_ecc_bits = (csr_internal_write_access_tx_ecc_bits_reg_tx_ecc_bits) ? csr_internal_bus_write_data[7:0]: csr_internal_field_tx_ecc_bits_reg_tx_ecc_bits; always @(posedge clock) if (reset) csr_internal_field_tx_ecc_bits_reg_tx_ecc_bits <= 8'h0; else csr_internal_field_tx_ecc_bits_reg_tx_ecc_bits <= csr_internal_next_field_tx_ecc_bits_reg_tx_ecc_bits; // // Register: tx_data_reg // Addressmap Offset: 0x440 // Access: read-write // assign csr_internal_read_data_tx_data_reg = csr_internal_field_tx_data_reg_tx_data_value & {16{csr_internal_decode_tx_data_reg}}; // Field: tx_data_reg.tx_data_value // Position: [15:0] // Access: read-write // Type: configuration assign csr_internal_write_access_tx_data_reg_tx_data_value = csr_internal_decode_tx_data_reg & csr_internal_write_access; assign csr_internal_next_field_tx_data_reg_tx_data_value = (csr_internal_write_access_tx_data_reg_tx_data_value) ? csr_internal_bus_write_data: csr_internal_field_tx_data_reg_tx_data_value; always @(posedge clock) csr_internal_field_tx_data_reg_tx_data_value <= csr_internal_next_field_tx_data_reg_tx_data_value; assign csr_internal_read_data = csr_internal_read_data_chip_config | csr_internal_read_data_ecc_cntrl_reg | csr_internal_read_data_ecc_int_reg | csr_internal_read_data_ecc_int_en_reg | csr_internal_read_data_ecc_err_addr_reg | csr_internal_read_data_diag_cntrl_reg | csr_internal_read_data_ecc_bits_reg | csr_internal_read_data_data_reg | csr_internal_read_data_rx_ecc_cntrl_reg | csr_internal_read_data_rx_ecc_int_reg | csr_internal_read_data_rx_ecc_int_en_reg | csr_internal_read_data_rx_ecc_err_addr_reg | csr_internal_read_data_rx_diag_cntrl_reg | csr_internal_read_data_rx_ecc_bits_reg | csr_internal_read_data_rx_data_reg | csr_internal_read_data_tx_ecc_cntrl_reg | csr_internal_read_data_tx_ecc_int_reg | csr_internal_read_data_tx_ecc_int_en_reg | csr_internal_read_data_tx_ecc_err_addr_reg | csr_internal_read_data_tx_diag_cntrl_reg | csr_internal_read_data_tx_ecc_bits_reg | csr_internal_read_data_tx_data_reg; endmodule