`include "./ecclegacy_ecc_legacy_testbench.v"
`include "./ecclegacy.vh"

module ecc_legacy_reset_diag();

reg [7:0] expected_8bit_lsb_0;
reg [15:0] expected_16bit_lsb_0;
reg [31:0] expected_32bit_lsb_0;
reg [63:0] expected_64bit_lsb_0;
reg [127:0] expected_128bit_lsb_0;
reg [0:7] expected_8bit_msb_0;
reg [0:15] expected_16bit_msb_0;
reg [0:31] expected_32bit_msb_0;
reg [0:63] expected_64bit_msb_0;
reg [0:127] expected_128bit_msb_0;
reg [15:0] readDataValue;
reg [15:0] tmpCsr;
integer  chkAddressError;
integer  chkReadAccessError;
integer  chkWriteAccessError;
integer  loopCount;

always @(negedge ecc_legacy_testbench.reset) begin: sim_block
  chkAddressError = 0;
  chkReadAccessError = 0;
  chkWriteAccessError = 0;

  $display("%d Start test for Reset values", $time);

  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h0, readDataValue);
  if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[0], readDataValue[0]);
  end
  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h80, readDataValue);
  if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[1], readDataValue[1]);
  end
  if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[0], readDataValue[0]);
  end
  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h9e, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h200, readDataValue);
  if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[1], readDataValue[1]);
  end
  if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[0], readDataValue[0]);
  end
  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h21e, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h400, readDataValue);
  if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[1], readDataValue[1]);
  end
  if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[0], readDataValue[0]);
  end
  expected_16bit_lsb_0 = 16'h0;
  readOp(11'h41e, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Check the read access error.", $time);
  chkReadAccessError = 1;
  chkReadAccessError = 0;

  $display("%d Check the write access error.", $time);
  chkWriteAccessError = 1;
  chkWriteAccessError = 0;
  #500; $finish;

end

task readOp;
  input[10:0] address;
  output[15:0] readDataValue;
  begin
    @(posedge ecc_legacy_testbench.clock);
    ecc_legacy_testbench.csr_address = address;
    ecc_legacy_testbench.csr_read_access = 1'b1;
    @(posedge ecc_legacy_testbench.clock);
    readDataValue = ecc_legacy_testbench.csr_read_data;
    ecc_legacy_testbench.csr_read_access = 1'b0;
  end
endtask

task writeOp;
  input[10:0] address;
  input[15:0] writeData;
  begin
    @(posedge ecc_legacy_testbench.clock);
    ecc_legacy_testbench.csr_address = address;
    ecc_legacy_testbench.csr_write_data = writeData;
    ecc_legacy_testbench.csr_write_access = 1'b1;
    @(posedge ecc_legacy_testbench.clock);
    ecc_legacy_testbench.csr_write_access = 1'b0;
  end
endtask

endmodule