// // Generated by Semifore, Inc. csrCompile // Version: 2008.03 // Released on: Aug 27 2008 10:15:22 // Verilog output // // Input file: C:\Documents and Settings\User\Desktop\semifore examples\block_ecc.csr // version: 2.1 // // Generated on: Wed Oct 01 17:58:08 2008 // by: User // // // Addressmap: ECC_regs // // Bus Protocol: Wishbone 3b // Bus combinatorial input and output // // Access: read-write // `timescale 1s / 1s module ECC_regs ( pckt_mem_regs_ecc_cntrl_reg_diag_en, pckt_mem_regs_ecc_cntrl_reg_correct_en, pckt_mem_regs_diag_cntrl_reg_initiate_trigger, pckt_mem_regs_diag_cntrl_reg_read, pckt_mem_regs_ecc_bits_reg_ecc_bits, rx_mem_regs_0_ecc_cntrl_reg_diag_en, rx_mem_regs_0_ecc_cntrl_reg_correct_en, rx_mem_regs_0_diag_cntrl_reg_initiate_trigger, rx_mem_regs_0_diag_cntrl_reg_read, rx_mem_regs_0_ecc_bits_reg_ecc_bits, rx_mem_regs_1_ecc_cntrl_reg_diag_en, rx_mem_regs_1_ecc_cntrl_reg_correct_en, rx_mem_regs_1_diag_cntrl_reg_initiate_trigger, rx_mem_regs_1_diag_cntrl_reg_read, rx_mem_regs_1_ecc_bits_reg_ecc_bits, rx_mem_regs_2_ecc_cntrl_reg_diag_en, rx_mem_regs_2_ecc_cntrl_reg_correct_en, rx_mem_regs_2_diag_cntrl_reg_initiate_trigger, rx_mem_regs_2_diag_cntrl_reg_read, rx_mem_regs_2_ecc_bits_reg_ecc_bits, rx_mem_regs_3_ecc_cntrl_reg_diag_en, rx_mem_regs_3_ecc_cntrl_reg_correct_en, rx_mem_regs_3_diag_cntrl_reg_initiate_trigger, rx_mem_regs_3_diag_cntrl_reg_read, rx_mem_regs_3_ecc_bits_reg_ecc_bits, tx_mem_regs_0_ecc_cntrl_reg_diag_en, tx_mem_regs_0_ecc_cntrl_reg_correct_en, tx_mem_regs_0_diag_cntrl_reg_initiate_trigger, tx_mem_regs_0_diag_cntrl_reg_read, tx_mem_regs_0_ecc_bits_reg_ecc_bits, tx_mem_regs_1_ecc_cntrl_reg_diag_en, tx_mem_regs_1_ecc_cntrl_reg_correct_en, tx_mem_regs_1_diag_cntrl_reg_initiate_trigger, tx_mem_regs_1_diag_cntrl_reg_read, tx_mem_regs_1_ecc_bits_reg_ecc_bits, tx_mem_regs_2_ecc_cntrl_reg_diag_en, tx_mem_regs_2_ecc_cntrl_reg_correct_en, tx_mem_regs_2_diag_cntrl_reg_initiate_trigger, tx_mem_regs_2_diag_cntrl_reg_read, tx_mem_regs_2_ecc_bits_reg_ecc_bits, tx_mem_regs_3_ecc_cntrl_reg_diag_en, tx_mem_regs_3_ecc_cntrl_reg_correct_en, tx_mem_regs_3_diag_cntrl_reg_initiate_trigger, tx_mem_regs_3_diag_cntrl_reg_read, tx_mem_regs_3_ecc_bits_reg_ecc_bits, pkt_memory_address, pkt_memory_write_access, pkt_memory_write_data, ACK_O, DATA_O, pckt_mem_regs_ecc_int_reg_sbe_int_source, pckt_mem_regs_ecc_int_reg_mbe_int_source, pckt_mem_regs_ecc_err_addr_reg_address_load_enable, pckt_mem_regs_ecc_err_addr_reg_address_input, pckt_mem_regs_diag_cntrl_reg_initiate_clear, pckt_mem_regs_ecc_bits_reg_ecc_bits_load_enable, pckt_mem_regs_ecc_bits_reg_ecc_bits_input, pckt_mem_regs_data_reg_data_value_load_enable, pckt_mem_regs_data_reg_data_value_input, rx_mem_regs_0_ecc_int_reg_sbe_int_source, rx_mem_regs_0_ecc_int_reg_mbe_int_source, rx_mem_regs_0_ecc_err_addr_reg_address_load_enable, rx_mem_regs_0_ecc_err_addr_reg_address_input, rx_mem_regs_0_diag_cntrl_reg_initiate_clear, rx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable, rx_mem_regs_0_ecc_bits_reg_ecc_bits_input, rx_mem_regs_0_data_reg_data_value_load_enable, rx_mem_regs_0_data_reg_data_value_input, rx_mem_regs_1_ecc_int_reg_sbe_int_source, rx_mem_regs_1_ecc_int_reg_mbe_int_source, rx_mem_regs_1_ecc_err_addr_reg_address_load_enable, rx_mem_regs_1_ecc_err_addr_reg_address_input, rx_mem_regs_1_diag_cntrl_reg_initiate_clear, rx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable, rx_mem_regs_1_ecc_bits_reg_ecc_bits_input, rx_mem_regs_1_data_reg_data_value_load_enable, rx_mem_regs_1_data_reg_data_value_input, rx_mem_regs_2_ecc_int_reg_sbe_int_source, rx_mem_regs_2_ecc_int_reg_mbe_int_source, rx_mem_regs_2_ecc_err_addr_reg_address_load_enable, rx_mem_regs_2_ecc_err_addr_reg_address_input, rx_mem_regs_2_diag_cntrl_reg_initiate_clear, rx_mem_regs_2_ecc_bits_reg_ecc_bits_load_enable, rx_mem_regs_2_ecc_bits_reg_ecc_bits_input, rx_mem_regs_2_data_reg_data_value_load_enable, rx_mem_regs_2_data_reg_data_value_input, rx_mem_regs_3_ecc_int_reg_sbe_int_source, rx_mem_regs_3_ecc_int_reg_mbe_int_source, rx_mem_regs_3_ecc_err_addr_reg_address_load_enable, rx_mem_regs_3_ecc_err_addr_reg_address_input, rx_mem_regs_3_diag_cntrl_reg_initiate_clear, rx_mem_regs_3_ecc_bits_reg_ecc_bits_load_enable, rx_mem_regs_3_ecc_bits_reg_ecc_bits_input, rx_mem_regs_3_data_reg_data_value_load_enable, rx_mem_regs_3_data_reg_data_value_input, tx_mem_regs_0_ecc_int_reg_sbe_int_source, tx_mem_regs_0_ecc_int_reg_mbe_int_source, tx_mem_regs_0_ecc_err_addr_reg_address_load_enable, tx_mem_regs_0_ecc_err_addr_reg_address_input, tx_mem_regs_0_diag_cntrl_reg_initiate_clear, tx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable, tx_mem_regs_0_ecc_bits_reg_ecc_bits_input, tx_mem_regs_0_data_reg_data_value_load_enable, tx_mem_regs_0_data_reg_data_value_input, tx_mem_regs_1_ecc_int_reg_sbe_int_source, tx_mem_regs_1_ecc_int_reg_mbe_int_source, tx_mem_regs_1_ecc_err_addr_reg_address_load_enable, tx_mem_regs_1_ecc_err_addr_reg_address_input, tx_mem_regs_1_diag_cntrl_reg_initiate_clear, tx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable, tx_mem_regs_1_ecc_bits_reg_ecc_bits_input, tx_mem_regs_1_data_reg_data_value_load_enable, tx_mem_regs_1_data_reg_data_value_input, tx_mem_regs_2_ecc_int_reg_sbe_int_source, tx_mem_regs_2_ecc_int_reg_mbe_int_source, tx_mem_regs_2_ecc_err_addr_reg_address_load_enable, tx_mem_regs_2_ecc_err_addr_reg_address_input, tx_mem_regs_2_diag_cntrl_reg_initiate_clear, tx_mem_regs_2_ecc_bits_reg_ecc_bits_load_enable, tx_mem_regs_2_ecc_bits_reg_ecc_bits_input, tx_mem_regs_2_data_reg_data_value_load_enable, tx_mem_regs_2_data_reg_data_value_input, tx_mem_regs_3_ecc_int_reg_sbe_int_source, tx_mem_regs_3_ecc_int_reg_mbe_int_source, tx_mem_regs_3_ecc_err_addr_reg_address_load_enable, tx_mem_regs_3_ecc_err_addr_reg_address_input, tx_mem_regs_3_diag_cntrl_reg_initiate_clear, tx_mem_regs_3_ecc_bits_reg_ecc_bits_load_enable, tx_mem_regs_3_ecc_bits_reg_ecc_bits_input, tx_mem_regs_3_data_reg_data_value_load_enable, tx_mem_regs_3_data_reg_data_value_input, pkt_memory_ready, pkt_memory_read_data, STB_I, WE_I, CYC_I, ADR_I, DATA_I, RST_I, CLK_I ); output pckt_mem_regs_ecc_cntrl_reg_diag_en; output pckt_mem_regs_ecc_cntrl_reg_correct_en; output pckt_mem_regs_diag_cntrl_reg_initiate_trigger; output pckt_mem_regs_diag_cntrl_reg_read; output [5:0] pckt_mem_regs_ecc_bits_reg_ecc_bits; output rx_mem_regs_0_ecc_cntrl_reg_diag_en; output rx_mem_regs_0_ecc_cntrl_reg_correct_en; output rx_mem_regs_0_diag_cntrl_reg_initiate_trigger; output rx_mem_regs_0_diag_cntrl_reg_read; output [5:0] rx_mem_regs_0_ecc_bits_reg_ecc_bits; output rx_mem_regs_1_ecc_cntrl_reg_diag_en; output rx_mem_regs_1_ecc_cntrl_reg_correct_en; output rx_mem_regs_1_diag_cntrl_reg_initiate_trigger; output rx_mem_regs_1_diag_cntrl_reg_read; output [5:0] rx_mem_regs_1_ecc_bits_reg_ecc_bits; output rx_mem_regs_2_ecc_cntrl_reg_diag_en; output rx_mem_regs_2_ecc_cntrl_reg_correct_en; output rx_mem_regs_2_diag_cntrl_reg_initiate_trigger; output rx_mem_regs_2_diag_cntrl_reg_read; output [5:0] rx_mem_regs_2_ecc_bits_reg_ecc_bits; output rx_mem_regs_3_ecc_cntrl_reg_diag_en; output rx_mem_regs_3_ecc_cntrl_reg_correct_en; output rx_mem_regs_3_diag_cntrl_reg_initiate_trigger; output rx_mem_regs_3_diag_cntrl_reg_read; output [5:0] rx_mem_regs_3_ecc_bits_reg_ecc_bits; output tx_mem_regs_0_ecc_cntrl_reg_diag_en; output tx_mem_regs_0_ecc_cntrl_reg_correct_en; output tx_mem_regs_0_diag_cntrl_reg_initiate_trigger; output tx_mem_regs_0_diag_cntrl_reg_read; output [5:0] tx_mem_regs_0_ecc_bits_reg_ecc_bits; output tx_mem_regs_1_ecc_cntrl_reg_diag_en; output tx_mem_regs_1_ecc_cntrl_reg_correct_en; output tx_mem_regs_1_diag_cntrl_reg_initiate_trigger; output tx_mem_regs_1_diag_cntrl_reg_read; output [5:0] tx_mem_regs_1_ecc_bits_reg_ecc_bits; output tx_mem_regs_2_ecc_cntrl_reg_diag_en; output tx_mem_regs_2_ecc_cntrl_reg_correct_en; output tx_mem_regs_2_diag_cntrl_reg_initiate_trigger; output tx_mem_regs_2_diag_cntrl_reg_read; output [5:0] tx_mem_regs_2_ecc_bits_reg_ecc_bits; output tx_mem_regs_3_ecc_cntrl_reg_diag_en; output tx_mem_regs_3_ecc_cntrl_reg_correct_en; output tx_mem_regs_3_diag_cntrl_reg_initiate_trigger; output tx_mem_regs_3_diag_cntrl_reg_read; output [5:0] tx_mem_regs_3_ecc_bits_reg_ecc_bits; output [13:0] pkt_memory_address; output pkt_memory_write_access; output [15:0] pkt_memory_write_data; output ACK_O; output [15:0] DATA_O; input pckt_mem_regs_ecc_int_reg_sbe_int_source; input pckt_mem_regs_ecc_int_reg_mbe_int_source; input pckt_mem_regs_ecc_err_addr_reg_address_load_enable; input [13:0] pckt_mem_regs_ecc_err_addr_reg_address_input; input pckt_mem_regs_diag_cntrl_reg_initiate_clear; input pckt_mem_regs_ecc_bits_reg_ecc_bits_load_enable; input [5:0] pckt_mem_regs_ecc_bits_reg_ecc_bits_input; input pckt_mem_regs_data_reg_data_value_load_enable; input [15:0] pckt_mem_regs_data_reg_data_value_input; input rx_mem_regs_0_ecc_int_reg_sbe_int_source; input rx_mem_regs_0_ecc_int_reg_mbe_int_source; input rx_mem_regs_0_ecc_err_addr_reg_address_load_enable; input [13:0] rx_mem_regs_0_ecc_err_addr_reg_address_input; input rx_mem_regs_0_diag_cntrl_reg_initiate_clear; input rx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable; input [5:0] rx_mem_regs_0_ecc_bits_reg_ecc_bits_input; input rx_mem_regs_0_data_reg_data_value_load_enable; input [15:0] rx_mem_regs_0_data_reg_data_value_input; input rx_mem_regs_1_ecc_int_reg_sbe_int_source; input rx_mem_regs_1_ecc_int_reg_mbe_int_source; input rx_mem_regs_1_ecc_err_addr_reg_address_load_enable; input [13:0] rx_mem_regs_1_ecc_err_addr_reg_address_input; input rx_mem_regs_1_diag_cntrl_reg_initiate_clear; input rx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable; input [5:0] rx_mem_regs_1_ecc_bits_reg_ecc_bits_input; input rx_mem_regs_1_data_reg_data_value_load_enable; input [15:0] rx_mem_regs_1_data_reg_data_value_input; input rx_mem_regs_2_ecc_int_reg_sbe_int_source; input rx_mem_regs_2_ecc_int_reg_mbe_int_source; input rx_mem_regs_2_ecc_err_addr_reg_address_load_enable; input [13:0] rx_mem_regs_2_ecc_err_addr_reg_address_input; input rx_mem_regs_2_diag_cntrl_reg_initiate_clear; input rx_mem_regs_2_ecc_bits_reg_ecc_bits_load_enable; input [5:0] rx_mem_regs_2_ecc_bits_reg_ecc_bits_input; input rx_mem_regs_2_data_reg_data_value_load_enable; input [15:0] rx_mem_regs_2_data_reg_data_value_input; input rx_mem_regs_3_ecc_int_reg_sbe_int_source; input rx_mem_regs_3_ecc_int_reg_mbe_int_source; input rx_mem_regs_3_ecc_err_addr_reg_address_load_enable; input [13:0] rx_mem_regs_3_ecc_err_addr_reg_address_input; input rx_mem_regs_3_diag_cntrl_reg_initiate_clear; input rx_mem_regs_3_ecc_bits_reg_ecc_bits_load_enable; input [5:0] rx_mem_regs_3_ecc_bits_reg_ecc_bits_input; input rx_mem_regs_3_data_reg_data_value_load_enable; input [15:0] rx_mem_regs_3_data_reg_data_value_input; input tx_mem_regs_0_ecc_int_reg_sbe_int_source; input tx_mem_regs_0_ecc_int_reg_mbe_int_source; input tx_mem_regs_0_ecc_err_addr_reg_address_load_enable; input [13:0] tx_mem_regs_0_ecc_err_addr_reg_address_input; input tx_mem_regs_0_diag_cntrl_reg_initiate_clear; input tx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable; input [5:0] tx_mem_regs_0_ecc_bits_reg_ecc_bits_input; input tx_mem_regs_0_data_reg_data_value_load_enable; input [15:0] tx_mem_regs_0_data_reg_data_value_input; input tx_mem_regs_1_ecc_int_reg_sbe_int_source; input tx_mem_regs_1_ecc_int_reg_mbe_int_source; input tx_mem_regs_1_ecc_err_addr_reg_address_load_enable; input [13:0] tx_mem_regs_1_ecc_err_addr_reg_address_input; input tx_mem_regs_1_diag_cntrl_reg_initiate_clear; input tx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable; input [5:0] tx_mem_regs_1_ecc_bits_reg_ecc_bits_input; input tx_mem_regs_1_data_reg_data_value_load_enable; input [15:0] tx_mem_regs_1_data_reg_data_value_input; input tx_mem_regs_2_ecc_int_reg_sbe_int_source; input tx_mem_regs_2_ecc_int_reg_mbe_int_source; input tx_mem_regs_2_ecc_err_addr_reg_address_load_enable; input [13:0] tx_mem_regs_2_ecc_err_addr_reg_address_input; input tx_mem_regs_2_diag_cntrl_reg_initiate_clear; input tx_mem_regs_2_ecc_bits_reg_ecc_bits_load_enable; input [5:0] tx_mem_regs_2_ecc_bits_reg_ecc_bits_input; input tx_mem_regs_2_data_reg_data_value_load_enable; input [15:0] tx_mem_regs_2_data_reg_data_value_input; input tx_mem_regs_3_ecc_int_reg_sbe_int_source; input tx_mem_regs_3_ecc_int_reg_mbe_int_source; input tx_mem_regs_3_ecc_err_addr_reg_address_load_enable; input [13:0] tx_mem_regs_3_ecc_err_addr_reg_address_input; input tx_mem_regs_3_diag_cntrl_reg_initiate_clear; input tx_mem_regs_3_ecc_bits_reg_ecc_bits_load_enable; input [5:0] tx_mem_regs_3_ecc_bits_reg_ecc_bits_input; input tx_mem_regs_3_data_reg_data_value_load_enable; input [15:0] tx_mem_regs_3_data_reg_data_value_input; input pkt_memory_ready; input [15:0] pkt_memory_read_data; input STB_I; input WE_I; input CYC_I; input [15:0] ADR_I; input [15:0] DATA_I; input RST_I; input CLK_I; // output wire declarations wire pckt_mem_regs_ecc_cntrl_reg_diag_en; wire pckt_mem_regs_ecc_cntrl_reg_correct_en; wire pckt_mem_regs_diag_cntrl_reg_initiate_trigger; wire pckt_mem_regs_diag_cntrl_reg_read; wire [5:0] pckt_mem_regs_ecc_bits_reg_ecc_bits; wire rx_mem_regs_0_ecc_cntrl_reg_diag_en; wire rx_mem_regs_0_ecc_cntrl_reg_correct_en; wire rx_mem_regs_0_diag_cntrl_reg_initiate_trigger; wire rx_mem_regs_0_diag_cntrl_reg_read; wire [5:0] rx_mem_regs_0_ecc_bits_reg_ecc_bits; wire rx_mem_regs_1_ecc_cntrl_reg_diag_en; wire rx_mem_regs_1_ecc_cntrl_reg_correct_en; wire rx_mem_regs_1_diag_cntrl_reg_initiate_trigger; wire rx_mem_regs_1_diag_cntrl_reg_read; wire [5:0] rx_mem_regs_1_ecc_bits_reg_ecc_bits; wire rx_mem_regs_2_ecc_cntrl_reg_diag_en; wire rx_mem_regs_2_ecc_cntrl_reg_correct_en; wire rx_mem_regs_2_diag_cntrl_reg_initiate_trigger; wire rx_mem_regs_2_diag_cntrl_reg_read; wire [5:0] rx_mem_regs_2_ecc_bits_reg_ecc_bits; wire rx_mem_regs_3_ecc_cntrl_reg_diag_en; wire rx_mem_regs_3_ecc_cntrl_reg_correct_en; wire rx_mem_regs_3_diag_cntrl_reg_initiate_trigger; wire rx_mem_regs_3_diag_cntrl_reg_read; wire [5:0] rx_mem_regs_3_ecc_bits_reg_ecc_bits; wire tx_mem_regs_0_ecc_cntrl_reg_diag_en; wire tx_mem_regs_0_ecc_cntrl_reg_correct_en; wire tx_mem_regs_0_diag_cntrl_reg_initiate_trigger; wire tx_mem_regs_0_diag_cntrl_reg_read; wire [5:0] tx_mem_regs_0_ecc_bits_reg_ecc_bits; wire tx_mem_regs_1_ecc_cntrl_reg_diag_en; wire tx_mem_regs_1_ecc_cntrl_reg_correct_en; wire tx_mem_regs_1_diag_cntrl_reg_initiate_trigger; wire tx_mem_regs_1_diag_cntrl_reg_read; wire [5:0] tx_mem_regs_1_ecc_bits_reg_ecc_bits; wire tx_mem_regs_2_ecc_cntrl_reg_diag_en; wire tx_mem_regs_2_ecc_cntrl_reg_correct_en; wire tx_mem_regs_2_diag_cntrl_reg_initiate_trigger; wire tx_mem_regs_2_diag_cntrl_reg_read; wire [5:0] tx_mem_regs_2_ecc_bits_reg_ecc_bits; wire tx_mem_regs_3_ecc_cntrl_reg_diag_en; wire tx_mem_regs_3_ecc_cntrl_reg_correct_en; wire tx_mem_regs_3_diag_cntrl_reg_initiate_trigger; wire tx_mem_regs_3_diag_cntrl_reg_read; wire [5:0] tx_mem_regs_3_ecc_bits_reg_ecc_bits; wire [13:0] pkt_memory_address; wire pkt_memory_write_access; wire [15:0] pkt_memory_write_data; wire ACK_O; wire [15:0] DATA_O; // input wire declarations wire pckt_mem_regs_ecc_int_reg_sbe_int_source; wire pckt_mem_regs_ecc_int_reg_mbe_int_source; wire pckt_mem_regs_ecc_err_addr_reg_address_load_enable; wire [13:0] pckt_mem_regs_ecc_err_addr_reg_address_input; wire pckt_mem_regs_diag_cntrl_reg_initiate_clear; wire pckt_mem_regs_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] pckt_mem_regs_ecc_bits_reg_ecc_bits_input; wire pckt_mem_regs_data_reg_data_value_load_enable; wire [15:0] pckt_mem_regs_data_reg_data_value_input; wire rx_mem_regs_0_ecc_int_reg_sbe_int_source; wire rx_mem_regs_0_ecc_int_reg_mbe_int_source; wire rx_mem_regs_0_ecc_err_addr_reg_address_load_enable; wire [13:0] rx_mem_regs_0_ecc_err_addr_reg_address_input; wire rx_mem_regs_0_diag_cntrl_reg_initiate_clear; wire rx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] rx_mem_regs_0_ecc_bits_reg_ecc_bits_input; wire rx_mem_regs_0_data_reg_data_value_load_enable; wire [15:0] rx_mem_regs_0_data_reg_data_value_input; wire rx_mem_regs_1_ecc_int_reg_sbe_int_source; wire rx_mem_regs_1_ecc_int_reg_mbe_int_source; wire rx_mem_regs_1_ecc_err_addr_reg_address_load_enable; wire [13:0] rx_mem_regs_1_ecc_err_addr_reg_address_input; wire rx_mem_regs_1_diag_cntrl_reg_initiate_clear; wire rx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] rx_mem_regs_1_ecc_bits_reg_ecc_bits_input; wire rx_mem_regs_1_data_reg_data_value_load_enable; wire [15:0] rx_mem_regs_1_data_reg_data_value_input; wire rx_mem_regs_2_ecc_int_reg_sbe_int_source; wire rx_mem_regs_2_ecc_int_reg_mbe_int_source; wire rx_mem_regs_2_ecc_err_addr_reg_address_load_enable; wire [13:0] rx_mem_regs_2_ecc_err_addr_reg_address_input; wire rx_mem_regs_2_diag_cntrl_reg_initiate_clear; wire rx_mem_regs_2_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] rx_mem_regs_2_ecc_bits_reg_ecc_bits_input; wire rx_mem_regs_2_data_reg_data_value_load_enable; wire [15:0] rx_mem_regs_2_data_reg_data_value_input; wire rx_mem_regs_3_ecc_int_reg_sbe_int_source; wire rx_mem_regs_3_ecc_int_reg_mbe_int_source; wire rx_mem_regs_3_ecc_err_addr_reg_address_load_enable; wire [13:0] rx_mem_regs_3_ecc_err_addr_reg_address_input; wire rx_mem_regs_3_diag_cntrl_reg_initiate_clear; wire rx_mem_regs_3_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] rx_mem_regs_3_ecc_bits_reg_ecc_bits_input; wire rx_mem_regs_3_data_reg_data_value_load_enable; wire [15:0] rx_mem_regs_3_data_reg_data_value_input; wire tx_mem_regs_0_ecc_int_reg_sbe_int_source; wire tx_mem_regs_0_ecc_int_reg_mbe_int_source; wire tx_mem_regs_0_ecc_err_addr_reg_address_load_enable; wire [13:0] tx_mem_regs_0_ecc_err_addr_reg_address_input; wire tx_mem_regs_0_diag_cntrl_reg_initiate_clear; wire tx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] tx_mem_regs_0_ecc_bits_reg_ecc_bits_input; wire tx_mem_regs_0_data_reg_data_value_load_enable; wire [15:0] tx_mem_regs_0_data_reg_data_value_input; wire tx_mem_regs_1_ecc_int_reg_sbe_int_source; wire tx_mem_regs_1_ecc_int_reg_mbe_int_source; wire tx_mem_regs_1_ecc_err_addr_reg_address_load_enable; wire [13:0] tx_mem_regs_1_ecc_err_addr_reg_address_input; wire tx_mem_regs_1_diag_cntrl_reg_initiate_clear; wire tx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] tx_mem_regs_1_ecc_bits_reg_ecc_bits_input; wire tx_mem_regs_1_data_reg_data_value_load_enable; wire [15:0] tx_mem_regs_1_data_reg_data_value_input; wire tx_mem_regs_2_ecc_int_reg_sbe_int_source; wire tx_mem_regs_2_ecc_int_reg_mbe_int_source; wire tx_mem_regs_2_ecc_err_addr_reg_address_load_enable; wire [13:0] tx_mem_regs_2_ecc_err_addr_reg_address_input; wire tx_mem_regs_2_diag_cntrl_reg_initiate_clear; wire tx_mem_regs_2_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] tx_mem_regs_2_ecc_bits_reg_ecc_bits_input; wire tx_mem_regs_2_data_reg_data_value_load_enable; wire [15:0] tx_mem_regs_2_data_reg_data_value_input; wire tx_mem_regs_3_ecc_int_reg_sbe_int_source; wire tx_mem_regs_3_ecc_int_reg_mbe_int_source; wire tx_mem_regs_3_ecc_err_addr_reg_address_load_enable; wire [13:0] tx_mem_regs_3_ecc_err_addr_reg_address_input; wire tx_mem_regs_3_diag_cntrl_reg_initiate_clear; wire tx_mem_regs_3_ecc_bits_reg_ecc_bits_load_enable; wire [5:0] tx_mem_regs_3_ecc_bits_reg_ecc_bits_input; wire tx_mem_regs_3_data_reg_data_value_load_enable; wire [15:0] tx_mem_regs_3_data_reg_data_value_input; wire pkt_memory_ready; wire [15:0] pkt_memory_read_data; wire STB_I; wire WE_I; wire CYC_I; wire [15:0] ADR_I; wire [15:0] DATA_I; wire RST_I; wire CLK_I; // internal net declarations reg csr_internal_field_chip_config_vpn_passthrough_enable; reg csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_diag_en; reg csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_correct_en; reg csr_internal_field_pckt_mem_regs_ecc_int_reg_sbe_int; reg csr_internal_field_pckt_mem_regs_ecc_int_reg_mbe_int; reg csr_internal_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_pckt_mem_regs_ecc_err_addr_reg_address; reg csr_internal_field_pckt_mem_regs_diag_cntrl_reg_initiate; reg csr_internal_trigger_pckt_mem_regs_diag_cntrl_reg_initiate; reg csr_internal_field_pckt_mem_regs_diag_cntrl_reg_read; reg [13:0] csr_internal_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_pckt_mem_regs_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_pckt_mem_regs_data_reg_data_value; reg csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en; reg csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en; reg csr_internal_field_rx_mem_regs_0_ecc_int_reg_sbe_int; reg csr_internal_field_rx_mem_regs_0_ecc_int_reg_mbe_int; reg csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_rx_mem_regs_0_ecc_err_addr_reg_address; reg csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_initiate; reg csr_internal_trigger_rx_mem_regs_0_diag_cntrl_reg_initiate; reg csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_read; reg [13:0] csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_rx_mem_regs_0_data_reg_data_value; reg csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en; reg csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en; reg csr_internal_field_rx_mem_regs_1_ecc_int_reg_sbe_int; reg csr_internal_field_rx_mem_regs_1_ecc_int_reg_mbe_int; reg csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_rx_mem_regs_1_ecc_err_addr_reg_address; reg csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_initiate; reg csr_internal_trigger_rx_mem_regs_1_diag_cntrl_reg_initiate; reg csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_read; reg [13:0] csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_rx_mem_regs_1_data_reg_data_value; reg csr_internal_field_rx_mem_regs_2_ecc_cntrl_reg_diag_en; reg csr_internal_field_rx_mem_regs_2_ecc_cntrl_reg_correct_en; reg csr_internal_field_rx_mem_regs_2_ecc_int_reg_sbe_int; reg csr_internal_field_rx_mem_regs_2_ecc_int_reg_mbe_int; reg csr_internal_field_rx_mem_regs_2_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_rx_mem_regs_2_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_rx_mem_regs_2_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_rx_mem_regs_2_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_rx_mem_regs_2_ecc_err_addr_reg_address; reg csr_internal_field_rx_mem_regs_2_diag_cntrl_reg_initiate; reg csr_internal_trigger_rx_mem_regs_2_diag_cntrl_reg_initiate; reg csr_internal_field_rx_mem_regs_2_diag_cntrl_reg_read; reg [13:0] csr_internal_field_rx_mem_regs_2_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_rx_mem_regs_2_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_rx_mem_regs_2_data_reg_data_value; reg csr_internal_field_rx_mem_regs_3_ecc_cntrl_reg_diag_en; reg csr_internal_field_rx_mem_regs_3_ecc_cntrl_reg_correct_en; reg csr_internal_field_rx_mem_regs_3_ecc_int_reg_sbe_int; reg csr_internal_field_rx_mem_regs_3_ecc_int_reg_mbe_int; reg csr_internal_field_rx_mem_regs_3_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_rx_mem_regs_3_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_rx_mem_regs_3_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_rx_mem_regs_3_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_rx_mem_regs_3_ecc_err_addr_reg_address; reg csr_internal_field_rx_mem_regs_3_diag_cntrl_reg_initiate; reg csr_internal_trigger_rx_mem_regs_3_diag_cntrl_reg_initiate; reg csr_internal_field_rx_mem_regs_3_diag_cntrl_reg_read; reg [13:0] csr_internal_field_rx_mem_regs_3_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_rx_mem_regs_3_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_rx_mem_regs_3_data_reg_data_value; reg csr_internal_field_tx_mem_regs_0_ecc_cntrl_reg_diag_en; reg csr_internal_field_tx_mem_regs_0_ecc_cntrl_reg_correct_en; reg csr_internal_field_tx_mem_regs_0_ecc_int_reg_sbe_int; reg csr_internal_field_tx_mem_regs_0_ecc_int_reg_mbe_int; reg csr_internal_field_tx_mem_regs_0_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_tx_mem_regs_0_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_tx_mem_regs_0_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_tx_mem_regs_0_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_tx_mem_regs_0_ecc_err_addr_reg_address; reg csr_internal_field_tx_mem_regs_0_diag_cntrl_reg_initiate; reg csr_internal_trigger_tx_mem_regs_0_diag_cntrl_reg_initiate; reg csr_internal_field_tx_mem_regs_0_diag_cntrl_reg_read; reg [13:0] csr_internal_field_tx_mem_regs_0_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_tx_mem_regs_0_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_tx_mem_regs_0_data_reg_data_value; reg csr_internal_field_tx_mem_regs_1_ecc_cntrl_reg_diag_en; reg csr_internal_field_tx_mem_regs_1_ecc_cntrl_reg_correct_en; reg csr_internal_field_tx_mem_regs_1_ecc_int_reg_sbe_int; reg csr_internal_field_tx_mem_regs_1_ecc_int_reg_mbe_int; reg csr_internal_field_tx_mem_regs_1_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_tx_mem_regs_1_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_tx_mem_regs_1_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_tx_mem_regs_1_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_tx_mem_regs_1_ecc_err_addr_reg_address; reg csr_internal_field_tx_mem_regs_1_diag_cntrl_reg_initiate; reg csr_internal_trigger_tx_mem_regs_1_diag_cntrl_reg_initiate; reg csr_internal_field_tx_mem_regs_1_diag_cntrl_reg_read; reg [13:0] csr_internal_field_tx_mem_regs_1_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_tx_mem_regs_1_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_tx_mem_regs_1_data_reg_data_value; reg csr_internal_field_tx_mem_regs_2_ecc_cntrl_reg_diag_en; reg csr_internal_field_tx_mem_regs_2_ecc_cntrl_reg_correct_en; reg csr_internal_field_tx_mem_regs_2_ecc_int_reg_sbe_int; reg csr_internal_field_tx_mem_regs_2_ecc_int_reg_mbe_int; reg csr_internal_field_tx_mem_regs_2_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_tx_mem_regs_2_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_tx_mem_regs_2_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_tx_mem_regs_2_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_tx_mem_regs_2_ecc_err_addr_reg_address; reg csr_internal_field_tx_mem_regs_2_diag_cntrl_reg_initiate; reg csr_internal_trigger_tx_mem_regs_2_diag_cntrl_reg_initiate; reg csr_internal_field_tx_mem_regs_2_diag_cntrl_reg_read; reg [13:0] csr_internal_field_tx_mem_regs_2_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_tx_mem_regs_2_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_tx_mem_regs_2_data_reg_data_value; reg csr_internal_field_tx_mem_regs_3_ecc_cntrl_reg_diag_en; reg csr_internal_field_tx_mem_regs_3_ecc_cntrl_reg_correct_en; reg csr_internal_field_tx_mem_regs_3_ecc_int_reg_sbe_int; reg csr_internal_field_tx_mem_regs_3_ecc_int_reg_mbe_int; reg csr_internal_field_tx_mem_regs_3_ecc_int_en_reg_sbe_int_en; reg csr_internal_field_tx_mem_regs_3_ecc_int_en_reg_mbe_int_en; reg [7:0] csr_internal_field_tx_mem_regs_3_int_cnt_reg_sbe_int_cnt; reg [7:0] csr_internal_field_tx_mem_regs_3_int_cnt_reg_mbe_int_cnt; reg [13:0] csr_internal_field_tx_mem_regs_3_ecc_err_addr_reg_address; reg csr_internal_field_tx_mem_regs_3_diag_cntrl_reg_initiate; reg csr_internal_trigger_tx_mem_regs_3_diag_cntrl_reg_initiate; reg csr_internal_field_tx_mem_regs_3_diag_cntrl_reg_read; reg [13:0] csr_internal_field_tx_mem_regs_3_diag_cntrl_reg_diagnostic_address; reg [5:0] csr_internal_field_tx_mem_regs_3_ecc_bits_reg_ecc_bits; reg [15:0] csr_internal_field_tx_mem_regs_3_data_reg_data_value; wire csr_internal_next_field_chip_config_vpn_passthrough_enable; wire csr_internal_write_access_chip_config_vpn_passthrough_enable; wire csr_internal_decode_chip_config; wire [15:0] csr_internal_read_data_chip_config; wire csr_internal_next_field_pckt_mem_regs_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_pckt_mem_regs_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_pckt_mem_regs_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_pckt_mem_regs_ecc_cntrl_reg_correct_en; wire csr_internal_decode_pckt_mem_regs_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_ecc_cntrl_reg; wire csr_internal_next_field_pckt_mem_regs_ecc_int_reg_sbe_int; wire csr_internal_write_access_pckt_mem_regs_ecc_int_reg_sbe_int; wire csr_internal_read_access_pckt_mem_regs_ecc_int_reg_sbe_int; wire csr_internal_next_field_pckt_mem_regs_ecc_int_reg_mbe_int; wire csr_internal_write_access_pckt_mem_regs_ecc_int_reg_mbe_int; wire csr_internal_read_access_pckt_mem_regs_ecc_int_reg_mbe_int; wire csr_internal_decode_pckt_mem_regs_ecc_int_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_ecc_int_reg; wire csr_internal_next_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_pckt_mem_regs_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_pckt_mem_regs_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_pckt_mem_regs_ecc_int_en_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_ecc_int_en_reg; wire [7:0] csr_internal_next_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_pckt_mem_regs_int_cnt_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_int_cnt_reg; wire [13:0] csr_internal_next_field_pckt_mem_regs_ecc_err_addr_reg_address; wire csr_internal_write_access_pckt_mem_regs_ecc_err_addr_reg_address; wire csr_internal_decode_pckt_mem_regs_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_ecc_err_addr_reg; wire csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_initiate; wire csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_pckt_mem_regs_diag_cntrl_reg_initiate; wire csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_read; wire csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_pckt_mem_regs_diag_cntrl_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_diag_cntrl_reg; wire [5:0] csr_internal_next_field_pckt_mem_regs_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_pckt_mem_regs_ecc_bits_reg_ecc_bits; wire csr_internal_decode_pckt_mem_regs_ecc_bits_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_ecc_bits_reg; wire [15:0] csr_internal_next_field_pckt_mem_regs_data_reg_data_value; wire csr_internal_write_access_pckt_mem_regs_data_reg_data_value; wire csr_internal_decode_pckt_mem_regs_data_reg; wire [15:0] csr_internal_read_data_pckt_mem_regs_data_reg; wire csr_internal_next_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_rx_mem_regs_0_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_rx_mem_regs_0_ecc_cntrl_reg_correct_en; wire csr_internal_decode_rx_mem_regs_0_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_ecc_cntrl_reg; wire csr_internal_next_field_rx_mem_regs_0_ecc_int_reg_sbe_int; wire csr_internal_write_access_rx_mem_regs_0_ecc_int_reg_sbe_int; wire csr_internal_read_access_rx_mem_regs_0_ecc_int_reg_sbe_int; wire csr_internal_next_field_rx_mem_regs_0_ecc_int_reg_mbe_int; wire csr_internal_write_access_rx_mem_regs_0_ecc_int_reg_mbe_int; wire csr_internal_read_access_rx_mem_regs_0_ecc_int_reg_mbe_int; wire csr_internal_decode_rx_mem_regs_0_ecc_int_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_ecc_int_reg; wire csr_internal_next_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_rx_mem_regs_0_ecc_int_en_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_ecc_int_en_reg; wire [7:0] csr_internal_next_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_rx_mem_regs_0_int_cnt_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_int_cnt_reg; wire [13:0] csr_internal_next_field_rx_mem_regs_0_ecc_err_addr_reg_address; wire csr_internal_write_access_rx_mem_regs_0_ecc_err_addr_reg_address; wire csr_internal_decode_rx_mem_regs_0_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_ecc_err_addr_reg; wire csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_initiate; wire csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_rx_mem_regs_0_diag_cntrl_reg_initiate; wire csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_read; wire csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_rx_mem_regs_0_diag_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_diag_cntrl_reg; wire [5:0] csr_internal_next_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_rx_mem_regs_0_ecc_bits_reg_ecc_bits; wire csr_internal_decode_rx_mem_regs_0_ecc_bits_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_ecc_bits_reg; wire [15:0] csr_internal_next_field_rx_mem_regs_0_data_reg_data_value; wire csr_internal_write_access_rx_mem_regs_0_data_reg_data_value; wire csr_internal_decode_rx_mem_regs_0_data_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_0_data_reg; wire csr_internal_next_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_rx_mem_regs_1_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_rx_mem_regs_1_ecc_cntrl_reg_correct_en; wire csr_internal_decode_rx_mem_regs_1_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_ecc_cntrl_reg; wire csr_internal_next_field_rx_mem_regs_1_ecc_int_reg_sbe_int; wire csr_internal_write_access_rx_mem_regs_1_ecc_int_reg_sbe_int; wire csr_internal_read_access_rx_mem_regs_1_ecc_int_reg_sbe_int; wire csr_internal_next_field_rx_mem_regs_1_ecc_int_reg_mbe_int; wire csr_internal_write_access_rx_mem_regs_1_ecc_int_reg_mbe_int; wire csr_internal_read_access_rx_mem_regs_1_ecc_int_reg_mbe_int; wire csr_internal_decode_rx_mem_regs_1_ecc_int_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_ecc_int_reg; wire csr_internal_next_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_rx_mem_regs_1_ecc_int_en_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_ecc_int_en_reg; wire [7:0] csr_internal_next_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_rx_mem_regs_1_int_cnt_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_int_cnt_reg; wire [13:0] csr_internal_next_field_rx_mem_regs_1_ecc_err_addr_reg_address; wire csr_internal_write_access_rx_mem_regs_1_ecc_err_addr_reg_address; wire csr_internal_decode_rx_mem_regs_1_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_ecc_err_addr_reg; wire csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_initiate; wire csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_rx_mem_regs_1_diag_cntrl_reg_initiate; wire csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_read; wire csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_rx_mem_regs_1_diag_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_diag_cntrl_reg; wire [5:0] csr_internal_next_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_rx_mem_regs_1_ecc_bits_reg_ecc_bits; wire csr_internal_decode_rx_mem_regs_1_ecc_bits_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_ecc_bits_reg; wire [15:0] csr_internal_next_field_rx_mem_regs_1_data_reg_data_value; wire csr_internal_write_access_rx_mem_regs_1_data_reg_data_value; wire csr_internal_decode_rx_mem_regs_1_data_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_1_data_reg; wire csr_internal_next_field_rx_mem_regs_2_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_rx_mem_regs_2_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_rx_mem_regs_2_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_rx_mem_regs_2_ecc_cntrl_reg_correct_en; wire csr_internal_decode_rx_mem_regs_2_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_ecc_cntrl_reg; wire csr_internal_next_field_rx_mem_regs_2_ecc_int_reg_sbe_int; wire csr_internal_write_access_rx_mem_regs_2_ecc_int_reg_sbe_int; wire csr_internal_read_access_rx_mem_regs_2_ecc_int_reg_sbe_int; wire csr_internal_next_field_rx_mem_regs_2_ecc_int_reg_mbe_int; wire csr_internal_write_access_rx_mem_regs_2_ecc_int_reg_mbe_int; wire csr_internal_read_access_rx_mem_regs_2_ecc_int_reg_mbe_int; wire csr_internal_decode_rx_mem_regs_2_ecc_int_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_ecc_int_reg; wire csr_internal_next_field_rx_mem_regs_2_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_rx_mem_regs_2_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_rx_mem_regs_2_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_rx_mem_regs_2_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_rx_mem_regs_2_ecc_int_en_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_ecc_int_en_reg; wire [7:0] csr_internal_next_field_rx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_rx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_rx_mem_regs_2_int_cnt_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_int_cnt_reg; wire [13:0] csr_internal_next_field_rx_mem_regs_2_ecc_err_addr_reg_address; wire csr_internal_write_access_rx_mem_regs_2_ecc_err_addr_reg_address; wire csr_internal_decode_rx_mem_regs_2_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_ecc_err_addr_reg; wire csr_internal_next_field_rx_mem_regs_2_diag_cntrl_reg_initiate; wire csr_internal_write_access_rx_mem_regs_2_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_rx_mem_regs_2_diag_cntrl_reg_initiate; wire csr_internal_next_field_rx_mem_regs_2_diag_cntrl_reg_read; wire csr_internal_write_access_rx_mem_regs_2_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_rx_mem_regs_2_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_rx_mem_regs_2_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_rx_mem_regs_2_diag_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_diag_cntrl_reg; wire [5:0] csr_internal_next_field_rx_mem_regs_2_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_rx_mem_regs_2_ecc_bits_reg_ecc_bits; wire csr_internal_decode_rx_mem_regs_2_ecc_bits_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_ecc_bits_reg; wire [15:0] csr_internal_next_field_rx_mem_regs_2_data_reg_data_value; wire csr_internal_write_access_rx_mem_regs_2_data_reg_data_value; wire csr_internal_decode_rx_mem_regs_2_data_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_2_data_reg; wire csr_internal_next_field_rx_mem_regs_3_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_rx_mem_regs_3_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_rx_mem_regs_3_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_rx_mem_regs_3_ecc_cntrl_reg_correct_en; wire csr_internal_decode_rx_mem_regs_3_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_ecc_cntrl_reg; wire csr_internal_next_field_rx_mem_regs_3_ecc_int_reg_sbe_int; wire csr_internal_write_access_rx_mem_regs_3_ecc_int_reg_sbe_int; wire csr_internal_read_access_rx_mem_regs_3_ecc_int_reg_sbe_int; wire csr_internal_next_field_rx_mem_regs_3_ecc_int_reg_mbe_int; wire csr_internal_write_access_rx_mem_regs_3_ecc_int_reg_mbe_int; wire csr_internal_read_access_rx_mem_regs_3_ecc_int_reg_mbe_int; wire csr_internal_decode_rx_mem_regs_3_ecc_int_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_ecc_int_reg; wire csr_internal_next_field_rx_mem_regs_3_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_rx_mem_regs_3_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_rx_mem_regs_3_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_rx_mem_regs_3_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_rx_mem_regs_3_ecc_int_en_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_ecc_int_en_reg; wire [7:0] csr_internal_next_field_rx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_rx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_rx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_rx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_rx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_rx_mem_regs_3_int_cnt_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_int_cnt_reg; wire [13:0] csr_internal_next_field_rx_mem_regs_3_ecc_err_addr_reg_address; wire csr_internal_write_access_rx_mem_regs_3_ecc_err_addr_reg_address; wire csr_internal_decode_rx_mem_regs_3_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_ecc_err_addr_reg; wire csr_internal_next_field_rx_mem_regs_3_diag_cntrl_reg_initiate; wire csr_internal_write_access_rx_mem_regs_3_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_rx_mem_regs_3_diag_cntrl_reg_initiate; wire csr_internal_next_field_rx_mem_regs_3_diag_cntrl_reg_read; wire csr_internal_write_access_rx_mem_regs_3_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_rx_mem_regs_3_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_rx_mem_regs_3_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_rx_mem_regs_3_diag_cntrl_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_diag_cntrl_reg; wire [5:0] csr_internal_next_field_rx_mem_regs_3_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_rx_mem_regs_3_ecc_bits_reg_ecc_bits; wire csr_internal_decode_rx_mem_regs_3_ecc_bits_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_ecc_bits_reg; wire [15:0] csr_internal_next_field_rx_mem_regs_3_data_reg_data_value; wire csr_internal_write_access_rx_mem_regs_3_data_reg_data_value; wire csr_internal_decode_rx_mem_regs_3_data_reg; wire [15:0] csr_internal_read_data_rx_mem_regs_3_data_reg; wire csr_internal_next_field_tx_mem_regs_0_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_tx_mem_regs_0_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_tx_mem_regs_0_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_tx_mem_regs_0_ecc_cntrl_reg_correct_en; wire csr_internal_decode_tx_mem_regs_0_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_ecc_cntrl_reg; wire csr_internal_next_field_tx_mem_regs_0_ecc_int_reg_sbe_int; wire csr_internal_write_access_tx_mem_regs_0_ecc_int_reg_sbe_int; wire csr_internal_read_access_tx_mem_regs_0_ecc_int_reg_sbe_int; wire csr_internal_next_field_tx_mem_regs_0_ecc_int_reg_mbe_int; wire csr_internal_write_access_tx_mem_regs_0_ecc_int_reg_mbe_int; wire csr_internal_read_access_tx_mem_regs_0_ecc_int_reg_mbe_int; wire csr_internal_decode_tx_mem_regs_0_ecc_int_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_ecc_int_reg; wire csr_internal_next_field_tx_mem_regs_0_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_tx_mem_regs_0_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_tx_mem_regs_0_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_tx_mem_regs_0_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_tx_mem_regs_0_ecc_int_en_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_ecc_int_en_reg; wire [7:0] csr_internal_next_field_tx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_0_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_tx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_0_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_tx_mem_regs_0_int_cnt_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_int_cnt_reg; wire [13:0] csr_internal_next_field_tx_mem_regs_0_ecc_err_addr_reg_address; wire csr_internal_write_access_tx_mem_regs_0_ecc_err_addr_reg_address; wire csr_internal_decode_tx_mem_regs_0_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_ecc_err_addr_reg; wire csr_internal_next_field_tx_mem_regs_0_diag_cntrl_reg_initiate; wire csr_internal_write_access_tx_mem_regs_0_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_tx_mem_regs_0_diag_cntrl_reg_initiate; wire csr_internal_next_field_tx_mem_regs_0_diag_cntrl_reg_read; wire csr_internal_write_access_tx_mem_regs_0_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_tx_mem_regs_0_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_tx_mem_regs_0_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_tx_mem_regs_0_diag_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_diag_cntrl_reg; wire [5:0] csr_internal_next_field_tx_mem_regs_0_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_tx_mem_regs_0_ecc_bits_reg_ecc_bits; wire csr_internal_decode_tx_mem_regs_0_ecc_bits_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_ecc_bits_reg; wire [15:0] csr_internal_next_field_tx_mem_regs_0_data_reg_data_value; wire csr_internal_write_access_tx_mem_regs_0_data_reg_data_value; wire csr_internal_decode_tx_mem_regs_0_data_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_0_data_reg; wire csr_internal_next_field_tx_mem_regs_1_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_tx_mem_regs_1_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_tx_mem_regs_1_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_tx_mem_regs_1_ecc_cntrl_reg_correct_en; wire csr_internal_decode_tx_mem_regs_1_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_ecc_cntrl_reg; wire csr_internal_next_field_tx_mem_regs_1_ecc_int_reg_sbe_int; wire csr_internal_write_access_tx_mem_regs_1_ecc_int_reg_sbe_int; wire csr_internal_read_access_tx_mem_regs_1_ecc_int_reg_sbe_int; wire csr_internal_next_field_tx_mem_regs_1_ecc_int_reg_mbe_int; wire csr_internal_write_access_tx_mem_regs_1_ecc_int_reg_mbe_int; wire csr_internal_read_access_tx_mem_regs_1_ecc_int_reg_mbe_int; wire csr_internal_decode_tx_mem_regs_1_ecc_int_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_ecc_int_reg; wire csr_internal_next_field_tx_mem_regs_1_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_tx_mem_regs_1_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_tx_mem_regs_1_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_tx_mem_regs_1_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_tx_mem_regs_1_ecc_int_en_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_ecc_int_en_reg; wire [7:0] csr_internal_next_field_tx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_1_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_tx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_1_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_tx_mem_regs_1_int_cnt_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_int_cnt_reg; wire [13:0] csr_internal_next_field_tx_mem_regs_1_ecc_err_addr_reg_address; wire csr_internal_write_access_tx_mem_regs_1_ecc_err_addr_reg_address; wire csr_internal_decode_tx_mem_regs_1_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_ecc_err_addr_reg; wire csr_internal_next_field_tx_mem_regs_1_diag_cntrl_reg_initiate; wire csr_internal_write_access_tx_mem_regs_1_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_tx_mem_regs_1_diag_cntrl_reg_initiate; wire csr_internal_next_field_tx_mem_regs_1_diag_cntrl_reg_read; wire csr_internal_write_access_tx_mem_regs_1_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_tx_mem_regs_1_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_tx_mem_regs_1_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_tx_mem_regs_1_diag_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_diag_cntrl_reg; wire [5:0] csr_internal_next_field_tx_mem_regs_1_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_tx_mem_regs_1_ecc_bits_reg_ecc_bits; wire csr_internal_decode_tx_mem_regs_1_ecc_bits_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_ecc_bits_reg; wire [15:0] csr_internal_next_field_tx_mem_regs_1_data_reg_data_value; wire csr_internal_write_access_tx_mem_regs_1_data_reg_data_value; wire csr_internal_decode_tx_mem_regs_1_data_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_1_data_reg; wire csr_internal_next_field_tx_mem_regs_2_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_tx_mem_regs_2_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_tx_mem_regs_2_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_tx_mem_regs_2_ecc_cntrl_reg_correct_en; wire csr_internal_decode_tx_mem_regs_2_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_ecc_cntrl_reg; wire csr_internal_next_field_tx_mem_regs_2_ecc_int_reg_sbe_int; wire csr_internal_write_access_tx_mem_regs_2_ecc_int_reg_sbe_int; wire csr_internal_read_access_tx_mem_regs_2_ecc_int_reg_sbe_int; wire csr_internal_next_field_tx_mem_regs_2_ecc_int_reg_mbe_int; wire csr_internal_write_access_tx_mem_regs_2_ecc_int_reg_mbe_int; wire csr_internal_read_access_tx_mem_regs_2_ecc_int_reg_mbe_int; wire csr_internal_decode_tx_mem_regs_2_ecc_int_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_ecc_int_reg; wire csr_internal_next_field_tx_mem_regs_2_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_tx_mem_regs_2_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_tx_mem_regs_2_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_tx_mem_regs_2_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_tx_mem_regs_2_ecc_int_en_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_ecc_int_en_reg; wire [7:0] csr_internal_next_field_tx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_2_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_tx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_2_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_tx_mem_regs_2_int_cnt_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_int_cnt_reg; wire [13:0] csr_internal_next_field_tx_mem_regs_2_ecc_err_addr_reg_address; wire csr_internal_write_access_tx_mem_regs_2_ecc_err_addr_reg_address; wire csr_internal_decode_tx_mem_regs_2_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_ecc_err_addr_reg; wire csr_internal_next_field_tx_mem_regs_2_diag_cntrl_reg_initiate; wire csr_internal_write_access_tx_mem_regs_2_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_tx_mem_regs_2_diag_cntrl_reg_initiate; wire csr_internal_next_field_tx_mem_regs_2_diag_cntrl_reg_read; wire csr_internal_write_access_tx_mem_regs_2_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_tx_mem_regs_2_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_tx_mem_regs_2_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_tx_mem_regs_2_diag_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_diag_cntrl_reg; wire [5:0] csr_internal_next_field_tx_mem_regs_2_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_tx_mem_regs_2_ecc_bits_reg_ecc_bits; wire csr_internal_decode_tx_mem_regs_2_ecc_bits_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_ecc_bits_reg; wire [15:0] csr_internal_next_field_tx_mem_regs_2_data_reg_data_value; wire csr_internal_write_access_tx_mem_regs_2_data_reg_data_value; wire csr_internal_decode_tx_mem_regs_2_data_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_2_data_reg; wire csr_internal_next_field_tx_mem_regs_3_ecc_cntrl_reg_diag_en; wire csr_internal_write_access_tx_mem_regs_3_ecc_cntrl_reg_diag_en; wire csr_internal_next_field_tx_mem_regs_3_ecc_cntrl_reg_correct_en; wire csr_internal_write_access_tx_mem_regs_3_ecc_cntrl_reg_correct_en; wire csr_internal_decode_tx_mem_regs_3_ecc_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_ecc_cntrl_reg; wire csr_internal_next_field_tx_mem_regs_3_ecc_int_reg_sbe_int; wire csr_internal_write_access_tx_mem_regs_3_ecc_int_reg_sbe_int; wire csr_internal_read_access_tx_mem_regs_3_ecc_int_reg_sbe_int; wire csr_internal_next_field_tx_mem_regs_3_ecc_int_reg_mbe_int; wire csr_internal_write_access_tx_mem_regs_3_ecc_int_reg_mbe_int; wire csr_internal_read_access_tx_mem_regs_3_ecc_int_reg_mbe_int; wire csr_internal_decode_tx_mem_regs_3_ecc_int_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_ecc_int_reg; wire csr_internal_next_field_tx_mem_regs_3_ecc_int_en_reg_sbe_int_en; wire csr_internal_write_access_tx_mem_regs_3_ecc_int_en_reg_sbe_int_en; wire csr_internal_next_field_tx_mem_regs_3_ecc_int_en_reg_mbe_int_en; wire csr_internal_write_access_tx_mem_regs_3_ecc_int_en_reg_mbe_int_en; wire csr_internal_decode_tx_mem_regs_3_ecc_int_en_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_ecc_int_en_reg; wire [7:0] csr_internal_next_field_tx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_3_int_cnt_reg_sbe_int_cnt; wire [7:0] csr_internal_next_field_tx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire csr_internal_write_access_tx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire csr_internal_read_access_tx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire [7:0] csr_internal_counter_input_tx_mem_regs_3_int_cnt_reg_mbe_int_cnt; wire csr_internal_decode_tx_mem_regs_3_int_cnt_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_int_cnt_reg; wire [13:0] csr_internal_next_field_tx_mem_regs_3_ecc_err_addr_reg_address; wire csr_internal_write_access_tx_mem_regs_3_ecc_err_addr_reg_address; wire csr_internal_decode_tx_mem_regs_3_ecc_err_addr_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_ecc_err_addr_reg; wire csr_internal_next_field_tx_mem_regs_3_diag_cntrl_reg_initiate; wire csr_internal_write_access_tx_mem_regs_3_diag_cntrl_reg_initiate; wire csr_internal_next_trigger_tx_mem_regs_3_diag_cntrl_reg_initiate; wire csr_internal_next_field_tx_mem_regs_3_diag_cntrl_reg_read; wire csr_internal_write_access_tx_mem_regs_3_diag_cntrl_reg_read; wire [13:0] csr_internal_next_field_tx_mem_regs_3_diag_cntrl_reg_diagnostic_address; wire csr_internal_write_access_tx_mem_regs_3_diag_cntrl_reg_diagnostic_address; wire csr_internal_decode_tx_mem_regs_3_diag_cntrl_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_diag_cntrl_reg; wire [5:0] csr_internal_next_field_tx_mem_regs_3_ecc_bits_reg_ecc_bits; wire csr_internal_write_access_tx_mem_regs_3_ecc_bits_reg_ecc_bits; wire csr_internal_decode_tx_mem_regs_3_ecc_bits_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_ecc_bits_reg; wire [15:0] csr_internal_next_field_tx_mem_regs_3_data_reg_data_value; wire csr_internal_write_access_tx_mem_regs_3_data_reg_data_value; wire csr_internal_decode_tx_mem_regs_3_data_reg; wire [15:0] csr_internal_read_data_tx_mem_regs_3_data_reg; wire csr_internal_decode_pkt_memory; wire [13:0] csr_internal_bus_address_pkt_memory; wire csr_internal_select_pkt_memory; wire csr_internal_bus_ready_pkt_memory; wire csr_internal_ready_pkt_memory; wire [15:0] csr_internal_read_data_pkt_memory; wire [15:0] csr_internal_bus_read_data_pkt_memory; wire csr_internal_write_access_pkt_memory; wire csr_internal_bus_write_access_pkt_memory; wire [15:0] csr_internal_bus_write_data_pkt_memory; wire csr_internal_bus_select; wire csr_internal_bus_write_command; wire csr_internal_bus_enable; wire csr_internal_bus_ready; wire csr_internal_external_decode; wire csr_internal_external_ready; wire [15:0] csr_internal_bus_address; wire [15:0] csr_internal_read_data; wire [15:0] csr_internal_bus_read_data; wire csr_internal_read_access; wire [15:0] csr_internal_bus_write_data; wire csr_internal_write_access; // Bus Protocol: Wishbone 3b // Bus combinatorial input and output assign csr_internal_bus_address = ADR_I; assign csr_internal_bus_select = STB_I; assign csr_internal_bus_write_command = WE_I; assign csr_internal_bus_enable = CYC_I; assign csr_internal_bus_write_data = DATA_I; assign ACK_O = csr_internal_bus_ready; assign DATA_O = csr_internal_bus_read_data; assign csr_internal_read_access = csr_internal_bus_select & csr_internal_bus_enable & (~csr_internal_bus_write_command); assign csr_internal_bus_read_data = (csr_internal_read_access) ? csr_internal_read_data: 16'b0; assign csr_internal_write_access = csr_internal_bus_select & csr_internal_bus_enable & csr_internal_bus_write_command; assign csr_internal_bus_ready = csr_internal_bus_select & csr_internal_bus_enable & csr_internal_external_ready; // Address Decode assign csr_internal_decode_chip_config = (csr_internal_bus_address[15:1] == 15'h0); assign csr_internal_decode_pckt_mem_regs_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h40); assign csr_internal_decode_pckt_mem_regs_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h41); assign csr_internal_decode_pckt_mem_regs_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h4c); assign csr_internal_decode_pckt_mem_regs_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h4d); assign csr_internal_decode_pckt_mem_regs_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h4e); assign csr_internal_decode_pckt_mem_regs_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h4f); assign csr_internal_decode_pckt_mem_regs_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h50); assign csr_internal_decode_pckt_mem_regs_data_reg = (csr_internal_bus_address[15:1] == 15'h60); assign csr_internal_decode_rx_mem_regs_0_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h100); assign csr_internal_decode_rx_mem_regs_0_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h101); assign csr_internal_decode_rx_mem_regs_0_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h10c); assign csr_internal_decode_rx_mem_regs_0_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h10d); assign csr_internal_decode_rx_mem_regs_0_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h10e); assign csr_internal_decode_rx_mem_regs_0_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h10f); assign csr_internal_decode_rx_mem_regs_0_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h110); assign csr_internal_decode_rx_mem_regs_0_data_reg = (csr_internal_bus_address[15:1] == 15'h120); assign csr_internal_decode_rx_mem_regs_1_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h140); assign csr_internal_decode_rx_mem_regs_1_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h141); assign csr_internal_decode_rx_mem_regs_1_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h14c); assign csr_internal_decode_rx_mem_regs_1_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h14d); assign csr_internal_decode_rx_mem_regs_1_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h14e); assign csr_internal_decode_rx_mem_regs_1_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h14f); assign csr_internal_decode_rx_mem_regs_1_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h150); assign csr_internal_decode_rx_mem_regs_1_data_reg = (csr_internal_bus_address[15:1] == 15'h160); assign csr_internal_decode_rx_mem_regs_2_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h180); assign csr_internal_decode_rx_mem_regs_2_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h181); assign csr_internal_decode_rx_mem_regs_2_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h18c); assign csr_internal_decode_rx_mem_regs_2_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h18d); assign csr_internal_decode_rx_mem_regs_2_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h18e); assign csr_internal_decode_rx_mem_regs_2_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h18f); assign csr_internal_decode_rx_mem_regs_2_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h190); assign csr_internal_decode_rx_mem_regs_2_data_reg = (csr_internal_bus_address[15:1] == 15'h1a0); assign csr_internal_decode_rx_mem_regs_3_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h1c0); assign csr_internal_decode_rx_mem_regs_3_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h1c1); assign csr_internal_decode_rx_mem_regs_3_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h1cc); assign csr_internal_decode_rx_mem_regs_3_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h1cd); assign csr_internal_decode_rx_mem_regs_3_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h1ce); assign csr_internal_decode_rx_mem_regs_3_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h1cf); assign csr_internal_decode_rx_mem_regs_3_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h1d0); assign csr_internal_decode_rx_mem_regs_3_data_reg = (csr_internal_bus_address[15:1] == 15'h1e0); assign csr_internal_decode_tx_mem_regs_0_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h200); assign csr_internal_decode_tx_mem_regs_0_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h201); assign csr_internal_decode_tx_mem_regs_0_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h20c); assign csr_internal_decode_tx_mem_regs_0_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h20d); assign csr_internal_decode_tx_mem_regs_0_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h20e); assign csr_internal_decode_tx_mem_regs_0_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h20f); assign csr_internal_decode_tx_mem_regs_0_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h210); assign csr_internal_decode_tx_mem_regs_0_data_reg = (csr_internal_bus_address[15:1] == 15'h220); assign csr_internal_decode_tx_mem_regs_1_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h240); assign csr_internal_decode_tx_mem_regs_1_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h241); assign csr_internal_decode_tx_mem_regs_1_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h24c); assign csr_internal_decode_tx_mem_regs_1_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h24d); assign csr_internal_decode_tx_mem_regs_1_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h24e); assign csr_internal_decode_tx_mem_regs_1_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h24f); assign csr_internal_decode_tx_mem_regs_1_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h250); assign csr_internal_decode_tx_mem_regs_1_data_reg = (csr_internal_bus_address[15:1] == 15'h260); assign csr_internal_decode_tx_mem_regs_2_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h280); assign csr_internal_decode_tx_mem_regs_2_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h281); assign csr_internal_decode_tx_mem_regs_2_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h28c); assign csr_internal_decode_tx_mem_regs_2_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h28d); assign csr_internal_decode_tx_mem_regs_2_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h28e); assign csr_internal_decode_tx_mem_regs_2_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h28f); assign csr_internal_decode_tx_mem_regs_2_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h290); assign csr_internal_decode_tx_mem_regs_2_data_reg = (csr_internal_bus_address[15:1] == 15'h2a0); assign csr_internal_decode_tx_mem_regs_3_ecc_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h2c0); assign csr_internal_decode_tx_mem_regs_3_ecc_int_reg = (csr_internal_bus_address[15:1] == 15'h2c1); assign csr_internal_decode_tx_mem_regs_3_ecc_int_en_reg = (csr_internal_bus_address[15:1] == 15'h2cc); assign csr_internal_decode_tx_mem_regs_3_int_cnt_reg = (csr_internal_bus_address[15:1] == 15'h2cd); assign csr_internal_decode_tx_mem_regs_3_ecc_err_addr_reg = (csr_internal_bus_address[15:1] == 15'h2ce); assign csr_internal_decode_tx_mem_regs_3_diag_cntrl_reg = (csr_internal_bus_address[15:1] == 15'h2cf); assign csr_internal_decode_tx_mem_regs_3_ecc_bits_reg = (csr_internal_bus_address[15:1] == 15'h2d0); assign csr_internal_decode_tx_mem_regs_3_data_reg = (csr_internal_bus_address[15:1] == 15'h2e0); assign csr_internal_decode_pkt_memory = (csr_internal_bus_address[15] == 1'h1); assign csr_internal_external_decode = csr_internal_decode_pkt_memory; // // Register: chip_config // Addressmap Offset: 0x0 // Access: read-write // assign csr_internal_read_data_chip_config = { 15'h0, csr_internal_field_chip_config_vpn_passthrough_enable } & {16{csr_internal_decode_chip_config}}; // Field: chip_config.vpn_passthrough_enable // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_chip_config_vpn_passthrough_enable = csr_internal_decode_chip_config & csr_internal_write_access; assign csr_internal_next_field_chip_config_vpn_passthrough_enable = (csr_internal_write_access_chip_config_vpn_passthrough_enable) ? csr_internal_bus_write_data[0]: csr_internal_field_chip_config_vpn_passthrough_enable; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_chip_config_vpn_passthrough_enable <= 1'h0; else csr_internal_field_chip_config_vpn_passthrough_enable <= csr_internal_next_field_chip_config_vpn_passthrough_enable; // // Register: pckt_mem_regs.ecc_cntrl_reg // Addressmap Offset: 0x80 // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_ecc_cntrl_reg = { 14'h0, csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_diag_en, csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_correct_en } & {16{csr_internal_decode_pckt_mem_regs_ecc_cntrl_reg}}; // Field: pckt_mem_regs.ecc_cntrl_reg.diag_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_ecc_cntrl_reg_diag_en = csr_internal_decode_pckt_mem_regs_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_cntrl_reg_diag_en = (csr_internal_write_access_pckt_mem_regs_ecc_cntrl_reg_diag_en) ? csr_internal_bus_write_data[1]: csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_diag_en; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_diag_en <= 1'b0; else csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_diag_en <= csr_internal_next_field_pckt_mem_regs_ecc_cntrl_reg_diag_en; assign pckt_mem_regs_ecc_cntrl_reg_diag_en = csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_diag_en; // Field: pckt_mem_regs.ecc_cntrl_reg.correct_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_ecc_cntrl_reg_correct_en = csr_internal_decode_pckt_mem_regs_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_cntrl_reg_correct_en = (csr_internal_write_access_pckt_mem_regs_ecc_cntrl_reg_correct_en) ? csr_internal_bus_write_data[0]: csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_correct_en; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_correct_en <= 1'b0; else csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_correct_en <= csr_internal_next_field_pckt_mem_regs_ecc_cntrl_reg_correct_en; assign pckt_mem_regs_ecc_cntrl_reg_correct_en = csr_internal_field_pckt_mem_regs_ecc_cntrl_reg_correct_en; // // Register: pckt_mem_regs.ecc_int_reg // Addressmap Offset: 0x82 // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_ecc_int_reg = { 14'h0, csr_internal_field_pckt_mem_regs_ecc_int_reg_sbe_int, csr_internal_field_pckt_mem_regs_ecc_int_reg_mbe_int } & {16{csr_internal_decode_pckt_mem_regs_ecc_int_reg}}; // Field: pckt_mem_regs.ecc_int_reg.sbe_int // Position: [1] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_pckt_mem_regs_ecc_int_reg_sbe_int = csr_internal_decode_pckt_mem_regs_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_pckt_mem_regs_ecc_int_reg_sbe_int = csr_internal_decode_pckt_mem_regs_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_int_reg_sbe_int = (csr_internal_write_access_pckt_mem_regs_ecc_int_reg_sbe_int) ? csr_internal_bus_write_data[1]: (pckt_mem_regs_ecc_int_reg_sbe_int_source) ? 1'b1: (csr_internal_read_access_pckt_mem_regs_ecc_int_reg_sbe_int) ? 1'b0: csr_internal_field_pckt_mem_regs_ecc_int_reg_sbe_int; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_ecc_int_reg_sbe_int <= csr_internal_next_field_pckt_mem_regs_ecc_int_reg_sbe_int; // Field: pckt_mem_regs.ecc_int_reg.mbe_int // Position: [0] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_pckt_mem_regs_ecc_int_reg_mbe_int = csr_internal_decode_pckt_mem_regs_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_pckt_mem_regs_ecc_int_reg_mbe_int = csr_internal_decode_pckt_mem_regs_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_int_reg_mbe_int = (csr_internal_write_access_pckt_mem_regs_ecc_int_reg_mbe_int) ? csr_internal_bus_write_data[0]: (pckt_mem_regs_ecc_int_reg_mbe_int_source) ? 1'b1: (csr_internal_read_access_pckt_mem_regs_ecc_int_reg_mbe_int) ? 1'b0: csr_internal_field_pckt_mem_regs_ecc_int_reg_mbe_int; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_ecc_int_reg_mbe_int <= csr_internal_next_field_pckt_mem_regs_ecc_int_reg_mbe_int; // // Register: pckt_mem_regs.ecc_int_en_reg // Addressmap Offset: 0x98 // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_ecc_int_en_reg = { 14'h0, csr_internal_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en, csr_internal_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en } & {16{csr_internal_decode_pckt_mem_regs_ecc_int_en_reg}}; // Field: pckt_mem_regs.ecc_int_en_reg.sbe_int_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_ecc_int_en_reg_sbe_int_en = csr_internal_decode_pckt_mem_regs_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en = (csr_internal_write_access_pckt_mem_regs_ecc_int_en_reg_sbe_int_en) ? csr_internal_bus_write_data[1]: csr_internal_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en <= csr_internal_next_field_pckt_mem_regs_ecc_int_en_reg_sbe_int_en; // Field: pckt_mem_regs.ecc_int_en_reg.mbe_int_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_ecc_int_en_reg_mbe_int_en = csr_internal_decode_pckt_mem_regs_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en = (csr_internal_write_access_pckt_mem_regs_ecc_int_en_reg_mbe_int_en) ? csr_internal_bus_write_data[0]: csr_internal_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en <= csr_internal_next_field_pckt_mem_regs_ecc_int_en_reg_mbe_int_en; // // Register: pckt_mem_regs.int_cnt_reg // Addressmap Offset: 0x9a // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_int_cnt_reg = { csr_internal_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt, csr_internal_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt } & {16{csr_internal_decode_pckt_mem_regs_int_cnt_reg}}; // Field: pckt_mem_regs.int_cnt_reg.sbe_int_cnt // Position: [15:8] // Access: read-write // Read Effect: clear // Type: counter assign csr_internal_read_access_pckt_mem_regs_int_cnt_reg_sbe_int_cnt = csr_internal_decode_pckt_mem_regs_int_cnt_reg & csr_internal_read_access; assign csr_internal_write_access_pckt_mem_regs_int_cnt_reg_sbe_int_cnt = csr_internal_decode_pckt_mem_regs_int_cnt_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt = (csr_internal_write_access_pckt_mem_regs_int_cnt_reg_sbe_int_cnt) ? csr_internal_bus_write_data[15:8]: (pckt_mem_regs_ecc_int_reg_sbe_int_source) ? (csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_sbe_int_cnt + 8'b1): csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; assign csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_sbe_int_cnt = (csr_internal_read_access_pckt_mem_regs_int_cnt_reg_sbe_int_cnt) ? 8'b0: csr_internal_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt <= csr_internal_next_field_pckt_mem_regs_int_cnt_reg_sbe_int_cnt; // Field: pckt_mem_regs.int_cnt_reg.mbe_int_cnt // Position: [7:0] // Access: read-write // Read Effect: clear // Type: counter assign csr_internal_read_access_pckt_mem_regs_int_cnt_reg_mbe_int_cnt = csr_internal_decode_pckt_mem_regs_int_cnt_reg & csr_internal_read_access; assign csr_internal_write_access_pckt_mem_regs_int_cnt_reg_mbe_int_cnt = csr_internal_decode_pckt_mem_regs_int_cnt_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt = (csr_internal_write_access_pckt_mem_regs_int_cnt_reg_mbe_int_cnt) ? csr_internal_bus_write_data[7:0]: (pckt_mem_regs_ecc_int_reg_mbe_int_source) ? (csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_mbe_int_cnt + 8'b1): csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; assign csr_internal_counter_input_pckt_mem_regs_int_cnt_reg_mbe_int_cnt = (csr_internal_read_access_pckt_mem_regs_int_cnt_reg_mbe_int_cnt) ? 8'b0: csr_internal_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt <= csr_internal_next_field_pckt_mem_regs_int_cnt_reg_mbe_int_cnt; // // Register: pckt_mem_regs.ecc_err_addr_reg // Addressmap Offset: 0x9c // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_ecc_err_addr_reg = { 2'h0, csr_internal_field_pckt_mem_regs_ecc_err_addr_reg_address } & {16{csr_internal_decode_pckt_mem_regs_ecc_err_addr_reg}}; // Field: pckt_mem_regs.ecc_err_addr_reg.address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_ecc_err_addr_reg_address = csr_internal_decode_pckt_mem_regs_ecc_err_addr_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_err_addr_reg_address = (csr_internal_write_access_pckt_mem_regs_ecc_err_addr_reg_address) ? csr_internal_bus_write_data[13:0]: (pckt_mem_regs_ecc_err_addr_reg_address_load_enable) ? pckt_mem_regs_ecc_err_addr_reg_address_input: csr_internal_field_pckt_mem_regs_ecc_err_addr_reg_address; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_ecc_err_addr_reg_address <= csr_internal_next_field_pckt_mem_regs_ecc_err_addr_reg_address; // // Register: pckt_mem_regs.diag_cntrl_reg // Addressmap Offset: 0x9e // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_diag_cntrl_reg = { csr_internal_field_pckt_mem_regs_diag_cntrl_reg_initiate, csr_internal_field_pckt_mem_regs_diag_cntrl_reg_read, csr_internal_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address } & {16{csr_internal_decode_pckt_mem_regs_diag_cntrl_reg}}; // Field: pckt_mem_regs.diag_cntrl_reg.initiate // Position: [15] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_initiate = csr_internal_decode_pckt_mem_regs_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_initiate = (csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_initiate) ? csr_internal_bus_write_data[15]: (pckt_mem_regs_diag_cntrl_reg_initiate_clear) ? 1'b0: csr_internal_field_pckt_mem_regs_diag_cntrl_reg_initiate; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_diag_cntrl_reg_initiate <= csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_initiate; assign csr_internal_next_trigger_pckt_mem_regs_diag_cntrl_reg_initiate = csr_internal_bus_write_data[15] & csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_initiate; always @(posedge CLK_I) csr_internal_trigger_pckt_mem_regs_diag_cntrl_reg_initiate <= csr_internal_next_trigger_pckt_mem_regs_diag_cntrl_reg_initiate; assign pckt_mem_regs_diag_cntrl_reg_initiate_trigger = csr_internal_trigger_pckt_mem_regs_diag_cntrl_reg_initiate; // Field: pckt_mem_regs.diag_cntrl_reg.read // Position: [14] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_read = csr_internal_decode_pckt_mem_regs_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_read = (csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_read) ? csr_internal_bus_write_data[14]: csr_internal_field_pckt_mem_regs_diag_cntrl_reg_read; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_diag_cntrl_reg_read <= csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_read; assign pckt_mem_regs_diag_cntrl_reg_read = csr_internal_field_pckt_mem_regs_diag_cntrl_reg_read; // Field: pckt_mem_regs.diag_cntrl_reg.diagnostic_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_diagnostic_address = csr_internal_decode_pckt_mem_regs_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address = (csr_internal_write_access_pckt_mem_regs_diag_cntrl_reg_diagnostic_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address <= csr_internal_next_field_pckt_mem_regs_diag_cntrl_reg_diagnostic_address; // // Register: pckt_mem_regs.ecc_bits_reg // Addressmap Offset: 0xa0 // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_ecc_bits_reg = { 10'h0, csr_internal_field_pckt_mem_regs_ecc_bits_reg_ecc_bits } & {16{csr_internal_decode_pckt_mem_regs_ecc_bits_reg}}; // Field: pckt_mem_regs.ecc_bits_reg.ecc_bits // Position: [5:0] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_ecc_bits_reg_ecc_bits = csr_internal_decode_pckt_mem_regs_ecc_bits_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_ecc_bits_reg_ecc_bits = (csr_internal_write_access_pckt_mem_regs_ecc_bits_reg_ecc_bits) ? csr_internal_bus_write_data[5:0]: (pckt_mem_regs_ecc_bits_reg_ecc_bits_load_enable) ? pckt_mem_regs_ecc_bits_reg_ecc_bits_input: csr_internal_field_pckt_mem_regs_ecc_bits_reg_ecc_bits; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_pckt_mem_regs_ecc_bits_reg_ecc_bits <= 6'b0; else csr_internal_field_pckt_mem_regs_ecc_bits_reg_ecc_bits <= csr_internal_next_field_pckt_mem_regs_ecc_bits_reg_ecc_bits; assign pckt_mem_regs_ecc_bits_reg_ecc_bits = csr_internal_field_pckt_mem_regs_ecc_bits_reg_ecc_bits; // // Register: pckt_mem_regs.data_reg // Addressmap Offset: 0xc0 // Access: read-write // assign csr_internal_read_data_pckt_mem_regs_data_reg = csr_internal_field_pckt_mem_regs_data_reg_data_value & {16{csr_internal_decode_pckt_mem_regs_data_reg}}; // Field: pckt_mem_regs.data_reg.data_value // Position: [15:0] // Access: read-write // Type: configuration assign csr_internal_write_access_pckt_mem_regs_data_reg_data_value = csr_internal_decode_pckt_mem_regs_data_reg & csr_internal_write_access; assign csr_internal_next_field_pckt_mem_regs_data_reg_data_value = (csr_internal_write_access_pckt_mem_regs_data_reg_data_value) ? csr_internal_bus_write_data: (pckt_mem_regs_data_reg_data_value_load_enable) ? pckt_mem_regs_data_reg_data_value_input: csr_internal_field_pckt_mem_regs_data_reg_data_value; always @(posedge CLK_I) csr_internal_field_pckt_mem_regs_data_reg_data_value <= csr_internal_next_field_pckt_mem_regs_data_reg_data_value; // // Register: rx_mem_regs[0].ecc_cntrl_reg // Addressmap Offset: 0x200 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_ecc_cntrl_reg = { 14'h0, csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en, csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en } & {16{csr_internal_decode_rx_mem_regs_0_ecc_cntrl_reg}}; // Field: rx_mem_regs[0].ecc_cntrl_reg.diag_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_ecc_cntrl_reg_diag_en = csr_internal_decode_rx_mem_regs_0_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en = (csr_internal_write_access_rx_mem_regs_0_ecc_cntrl_reg_diag_en) ? csr_internal_bus_write_data[1]: csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en <= 1'b0; else csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en <= csr_internal_next_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en; assign rx_mem_regs_0_ecc_cntrl_reg_diag_en = csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_diag_en; // Field: rx_mem_regs[0].ecc_cntrl_reg.correct_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_ecc_cntrl_reg_correct_en = csr_internal_decode_rx_mem_regs_0_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en = (csr_internal_write_access_rx_mem_regs_0_ecc_cntrl_reg_correct_en) ? csr_internal_bus_write_data[0]: csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en <= 1'b0; else csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en <= csr_internal_next_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en; assign rx_mem_regs_0_ecc_cntrl_reg_correct_en = csr_internal_field_rx_mem_regs_0_ecc_cntrl_reg_correct_en; // // Register: rx_mem_regs[0].ecc_int_reg // Addressmap Offset: 0x202 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_ecc_int_reg = { 14'h0, csr_internal_field_rx_mem_regs_0_ecc_int_reg_sbe_int, csr_internal_field_rx_mem_regs_0_ecc_int_reg_mbe_int } & {16{csr_internal_decode_rx_mem_regs_0_ecc_int_reg}}; // Field: rx_mem_regs[0].ecc_int_reg.sbe_int // Position: [1] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_rx_mem_regs_0_ecc_int_reg_sbe_int = csr_internal_decode_rx_mem_regs_0_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_0_ecc_int_reg_sbe_int = csr_internal_decode_rx_mem_regs_0_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_int_reg_sbe_int = (csr_internal_write_access_rx_mem_regs_0_ecc_int_reg_sbe_int) ? csr_internal_bus_write_data[1]: (rx_mem_regs_0_ecc_int_reg_sbe_int_source) ? 1'b1: (csr_internal_read_access_rx_mem_regs_0_ecc_int_reg_sbe_int) ? 1'b0: csr_internal_field_rx_mem_regs_0_ecc_int_reg_sbe_int; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_ecc_int_reg_sbe_int <= csr_internal_next_field_rx_mem_regs_0_ecc_int_reg_sbe_int; // Field: rx_mem_regs[0].ecc_int_reg.mbe_int // Position: [0] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_rx_mem_regs_0_ecc_int_reg_mbe_int = csr_internal_decode_rx_mem_regs_0_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_0_ecc_int_reg_mbe_int = csr_internal_decode_rx_mem_regs_0_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_int_reg_mbe_int = (csr_internal_write_access_rx_mem_regs_0_ecc_int_reg_mbe_int) ? csr_internal_bus_write_data[0]: (rx_mem_regs_0_ecc_int_reg_mbe_int_source) ? 1'b1: (csr_internal_read_access_rx_mem_regs_0_ecc_int_reg_mbe_int) ? 1'b0: csr_internal_field_rx_mem_regs_0_ecc_int_reg_mbe_int; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_ecc_int_reg_mbe_int <= csr_internal_next_field_rx_mem_regs_0_ecc_int_reg_mbe_int; // // Register: rx_mem_regs[0].ecc_int_en_reg // Addressmap Offset: 0x218 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_ecc_int_en_reg = { 14'h0, csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en, csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en } & {16{csr_internal_decode_rx_mem_regs_0_ecc_int_en_reg}}; // Field: rx_mem_regs[0].ecc_int_en_reg.sbe_int_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en = csr_internal_decode_rx_mem_regs_0_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en = (csr_internal_write_access_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en) ? csr_internal_bus_write_data[1]: csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en <= csr_internal_next_field_rx_mem_regs_0_ecc_int_en_reg_sbe_int_en; // Field: rx_mem_regs[0].ecc_int_en_reg.mbe_int_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en = csr_internal_decode_rx_mem_regs_0_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en = (csr_internal_write_access_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en) ? csr_internal_bus_write_data[0]: csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en <= csr_internal_next_field_rx_mem_regs_0_ecc_int_en_reg_mbe_int_en; // // Register: rx_mem_regs[0].int_cnt_reg // Addressmap Offset: 0x21a // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_int_cnt_reg = { csr_internal_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt, csr_internal_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt } & {16{csr_internal_decode_rx_mem_regs_0_int_cnt_reg}}; // Field: rx_mem_regs[0].int_cnt_reg.sbe_int_cnt // Position: [15:8] // Access: read-write // Read Effect: clear // Type: counter assign csr_internal_read_access_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt = csr_internal_decode_rx_mem_regs_0_int_cnt_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt = csr_internal_decode_rx_mem_regs_0_int_cnt_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt = (csr_internal_write_access_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt) ? csr_internal_bus_write_data[15:8]: (rx_mem_regs_0_ecc_int_reg_sbe_int_source) ? (csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt + 8'b1): csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; assign csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt = (csr_internal_read_access_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt) ? 8'b0: csr_internal_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt <= csr_internal_next_field_rx_mem_regs_0_int_cnt_reg_sbe_int_cnt; // Field: rx_mem_regs[0].int_cnt_reg.mbe_int_cnt // Position: [7:0] // Access: read-write // Read Effect: clear // Type: counter assign csr_internal_read_access_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt = csr_internal_decode_rx_mem_regs_0_int_cnt_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt = csr_internal_decode_rx_mem_regs_0_int_cnt_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt = (csr_internal_write_access_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt) ? csr_internal_bus_write_data[7:0]: (rx_mem_regs_0_ecc_int_reg_mbe_int_source) ? (csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt + 8'b1): csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; assign csr_internal_counter_input_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt = (csr_internal_read_access_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt) ? 8'b0: csr_internal_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt <= csr_internal_next_field_rx_mem_regs_0_int_cnt_reg_mbe_int_cnt; // // Register: rx_mem_regs[0].ecc_err_addr_reg // Addressmap Offset: 0x21c // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_ecc_err_addr_reg = { 2'h0, csr_internal_field_rx_mem_regs_0_ecc_err_addr_reg_address } & {16{csr_internal_decode_rx_mem_regs_0_ecc_err_addr_reg}}; // Field: rx_mem_regs[0].ecc_err_addr_reg.address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_ecc_err_addr_reg_address = csr_internal_decode_rx_mem_regs_0_ecc_err_addr_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_err_addr_reg_address = (csr_internal_write_access_rx_mem_regs_0_ecc_err_addr_reg_address) ? csr_internal_bus_write_data[13:0]: (rx_mem_regs_0_ecc_err_addr_reg_address_load_enable) ? rx_mem_regs_0_ecc_err_addr_reg_address_input: csr_internal_field_rx_mem_regs_0_ecc_err_addr_reg_address; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_ecc_err_addr_reg_address <= csr_internal_next_field_rx_mem_regs_0_ecc_err_addr_reg_address; // // Register: rx_mem_regs[0].diag_cntrl_reg // Addressmap Offset: 0x21e // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_diag_cntrl_reg = { csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_initiate, csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_read, csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address } & {16{csr_internal_decode_rx_mem_regs_0_diag_cntrl_reg}}; // Field: rx_mem_regs[0].diag_cntrl_reg.initiate // Position: [15] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_initiate = csr_internal_decode_rx_mem_regs_0_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_initiate = (csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_initiate) ? csr_internal_bus_write_data[15]: (rx_mem_regs_0_diag_cntrl_reg_initiate_clear) ? 1'b0: csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_initiate; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_initiate <= csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_initiate; assign csr_internal_next_trigger_rx_mem_regs_0_diag_cntrl_reg_initiate = csr_internal_bus_write_data[15] & csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_initiate; always @(posedge CLK_I) csr_internal_trigger_rx_mem_regs_0_diag_cntrl_reg_initiate <= csr_internal_next_trigger_rx_mem_regs_0_diag_cntrl_reg_initiate; assign rx_mem_regs_0_diag_cntrl_reg_initiate_trigger = csr_internal_trigger_rx_mem_regs_0_diag_cntrl_reg_initiate; // Field: rx_mem_regs[0].diag_cntrl_reg.read // Position: [14] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_read = csr_internal_decode_rx_mem_regs_0_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_read = (csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_read) ? csr_internal_bus_write_data[14]: csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_read; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_read <= csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_read; assign rx_mem_regs_0_diag_cntrl_reg_read = csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_read; // Field: rx_mem_regs[0].diag_cntrl_reg.diagnostic_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address = csr_internal_decode_rx_mem_regs_0_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address = (csr_internal_write_access_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address <= csr_internal_next_field_rx_mem_regs_0_diag_cntrl_reg_diagnostic_address; // // Register: rx_mem_regs[0].ecc_bits_reg // Addressmap Offset: 0x220 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_ecc_bits_reg = { 10'h0, csr_internal_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits } & {16{csr_internal_decode_rx_mem_regs_0_ecc_bits_reg}}; // Field: rx_mem_regs[0].ecc_bits_reg.ecc_bits // Position: [5:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_ecc_bits_reg_ecc_bits = csr_internal_decode_rx_mem_regs_0_ecc_bits_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits = (csr_internal_write_access_rx_mem_regs_0_ecc_bits_reg_ecc_bits) ? csr_internal_bus_write_data[5:0]: (rx_mem_regs_0_ecc_bits_reg_ecc_bits_load_enable) ? rx_mem_regs_0_ecc_bits_reg_ecc_bits_input: csr_internal_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits <= 6'b0; else csr_internal_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits <= csr_internal_next_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits; assign rx_mem_regs_0_ecc_bits_reg_ecc_bits = csr_internal_field_rx_mem_regs_0_ecc_bits_reg_ecc_bits; // // Register: rx_mem_regs[0].data_reg // Addressmap Offset: 0x240 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_0_data_reg = csr_internal_field_rx_mem_regs_0_data_reg_data_value & {16{csr_internal_decode_rx_mem_regs_0_data_reg}}; // Field: rx_mem_regs[0].data_reg.data_value // Position: [15:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_0_data_reg_data_value = csr_internal_decode_rx_mem_regs_0_data_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_0_data_reg_data_value = (csr_internal_write_access_rx_mem_regs_0_data_reg_data_value) ? csr_internal_bus_write_data: (rx_mem_regs_0_data_reg_data_value_load_enable) ? rx_mem_regs_0_data_reg_data_value_input: csr_internal_field_rx_mem_regs_0_data_reg_data_value; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_0_data_reg_data_value <= csr_internal_next_field_rx_mem_regs_0_data_reg_data_value; // // Register: rx_mem_regs[1].ecc_cntrl_reg // Addressmap Offset: 0x280 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_ecc_cntrl_reg = { 14'h0, csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en, csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en } & {16{csr_internal_decode_rx_mem_regs_1_ecc_cntrl_reg}}; // Field: rx_mem_regs[1].ecc_cntrl_reg.diag_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_ecc_cntrl_reg_diag_en = csr_internal_decode_rx_mem_regs_1_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en = (csr_internal_write_access_rx_mem_regs_1_ecc_cntrl_reg_diag_en) ? csr_internal_bus_write_data[1]: csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en <= 1'b0; else csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en <= csr_internal_next_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en; assign rx_mem_regs_1_ecc_cntrl_reg_diag_en = csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_diag_en; // Field: rx_mem_regs[1].ecc_cntrl_reg.correct_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_ecc_cntrl_reg_correct_en = csr_internal_decode_rx_mem_regs_1_ecc_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en = (csr_internal_write_access_rx_mem_regs_1_ecc_cntrl_reg_correct_en) ? csr_internal_bus_write_data[0]: csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en <= 1'b0; else csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en <= csr_internal_next_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en; assign rx_mem_regs_1_ecc_cntrl_reg_correct_en = csr_internal_field_rx_mem_regs_1_ecc_cntrl_reg_correct_en; // // Register: rx_mem_regs[1].ecc_int_reg // Addressmap Offset: 0x282 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_ecc_int_reg = { 14'h0, csr_internal_field_rx_mem_regs_1_ecc_int_reg_sbe_int, csr_internal_field_rx_mem_regs_1_ecc_int_reg_mbe_int } & {16{csr_internal_decode_rx_mem_regs_1_ecc_int_reg}}; // Field: rx_mem_regs[1].ecc_int_reg.sbe_int // Position: [1] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_rx_mem_regs_1_ecc_int_reg_sbe_int = csr_internal_decode_rx_mem_regs_1_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_1_ecc_int_reg_sbe_int = csr_internal_decode_rx_mem_regs_1_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_int_reg_sbe_int = (csr_internal_write_access_rx_mem_regs_1_ecc_int_reg_sbe_int) ? csr_internal_bus_write_data[1]: (rx_mem_regs_1_ecc_int_reg_sbe_int_source) ? 1'b1: (csr_internal_read_access_rx_mem_regs_1_ecc_int_reg_sbe_int) ? 1'b0: csr_internal_field_rx_mem_regs_1_ecc_int_reg_sbe_int; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_ecc_int_reg_sbe_int <= csr_internal_next_field_rx_mem_regs_1_ecc_int_reg_sbe_int; // Field: rx_mem_regs[1].ecc_int_reg.mbe_int // Position: [0] // Access: read-write // Read Effect: clear // Type: interrupt // Event: level assign csr_internal_read_access_rx_mem_regs_1_ecc_int_reg_mbe_int = csr_internal_decode_rx_mem_regs_1_ecc_int_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_1_ecc_int_reg_mbe_int = csr_internal_decode_rx_mem_regs_1_ecc_int_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_int_reg_mbe_int = (csr_internal_write_access_rx_mem_regs_1_ecc_int_reg_mbe_int) ? csr_internal_bus_write_data[0]: (rx_mem_regs_1_ecc_int_reg_mbe_int_source) ? 1'b1: (csr_internal_read_access_rx_mem_regs_1_ecc_int_reg_mbe_int) ? 1'b0: csr_internal_field_rx_mem_regs_1_ecc_int_reg_mbe_int; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_ecc_int_reg_mbe_int <= csr_internal_next_field_rx_mem_regs_1_ecc_int_reg_mbe_int; // // Register: rx_mem_regs[1].ecc_int_en_reg // Addressmap Offset: 0x298 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_ecc_int_en_reg = { 14'h0, csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en, csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en } & {16{csr_internal_decode_rx_mem_regs_1_ecc_int_en_reg}}; // Field: rx_mem_regs[1].ecc_int_en_reg.sbe_int_en // Position: [1] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en = csr_internal_decode_rx_mem_regs_1_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en = (csr_internal_write_access_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en) ? csr_internal_bus_write_data[1]: csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en <= csr_internal_next_field_rx_mem_regs_1_ecc_int_en_reg_sbe_int_en; // Field: rx_mem_regs[1].ecc_int_en_reg.mbe_int_en // Position: [0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en = csr_internal_decode_rx_mem_regs_1_ecc_int_en_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en = (csr_internal_write_access_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en) ? csr_internal_bus_write_data[0]: csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en <= csr_internal_next_field_rx_mem_regs_1_ecc_int_en_reg_mbe_int_en; // // Register: rx_mem_regs[1].int_cnt_reg // Addressmap Offset: 0x29a // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_int_cnt_reg = { csr_internal_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt, csr_internal_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt } & {16{csr_internal_decode_rx_mem_regs_1_int_cnt_reg}}; // Field: rx_mem_regs[1].int_cnt_reg.sbe_int_cnt // Position: [15:8] // Access: read-write // Read Effect: clear // Type: counter assign csr_internal_read_access_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt = csr_internal_decode_rx_mem_regs_1_int_cnt_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt = csr_internal_decode_rx_mem_regs_1_int_cnt_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt = (csr_internal_write_access_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt) ? csr_internal_bus_write_data[15:8]: (rx_mem_regs_1_ecc_int_reg_sbe_int_source) ? (csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt + 8'b1): csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; assign csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt = (csr_internal_read_access_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt) ? 8'b0: csr_internal_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt <= csr_internal_next_field_rx_mem_regs_1_int_cnt_reg_sbe_int_cnt; // Field: rx_mem_regs[1].int_cnt_reg.mbe_int_cnt // Position: [7:0] // Access: read-write // Read Effect: clear // Type: counter assign csr_internal_read_access_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt = csr_internal_decode_rx_mem_regs_1_int_cnt_reg & csr_internal_read_access; assign csr_internal_write_access_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt = csr_internal_decode_rx_mem_regs_1_int_cnt_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt = (csr_internal_write_access_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt) ? csr_internal_bus_write_data[7:0]: (rx_mem_regs_1_ecc_int_reg_mbe_int_source) ? (csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt + 8'b1): csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; assign csr_internal_counter_input_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt = (csr_internal_read_access_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt) ? 8'b0: csr_internal_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt <= csr_internal_next_field_rx_mem_regs_1_int_cnt_reg_mbe_int_cnt; // // Register: rx_mem_regs[1].ecc_err_addr_reg // Addressmap Offset: 0x29c // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_ecc_err_addr_reg = { 2'h0, csr_internal_field_rx_mem_regs_1_ecc_err_addr_reg_address } & {16{csr_internal_decode_rx_mem_regs_1_ecc_err_addr_reg}}; // Field: rx_mem_regs[1].ecc_err_addr_reg.address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_ecc_err_addr_reg_address = csr_internal_decode_rx_mem_regs_1_ecc_err_addr_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_err_addr_reg_address = (csr_internal_write_access_rx_mem_regs_1_ecc_err_addr_reg_address) ? csr_internal_bus_write_data[13:0]: (rx_mem_regs_1_ecc_err_addr_reg_address_load_enable) ? rx_mem_regs_1_ecc_err_addr_reg_address_input: csr_internal_field_rx_mem_regs_1_ecc_err_addr_reg_address; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_ecc_err_addr_reg_address <= csr_internal_next_field_rx_mem_regs_1_ecc_err_addr_reg_address; // // Register: rx_mem_regs[1].diag_cntrl_reg // Addressmap Offset: 0x29e // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_diag_cntrl_reg = { csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_initiate, csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_read, csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address } & {16{csr_internal_decode_rx_mem_regs_1_diag_cntrl_reg}}; // Field: rx_mem_regs[1].diag_cntrl_reg.initiate // Position: [15] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_initiate = csr_internal_decode_rx_mem_regs_1_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_initiate = (csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_initiate) ? csr_internal_bus_write_data[15]: (rx_mem_regs_1_diag_cntrl_reg_initiate_clear) ? 1'b0: csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_initiate; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_initiate <= csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_initiate; assign csr_internal_next_trigger_rx_mem_regs_1_diag_cntrl_reg_initiate = csr_internal_bus_write_data[15] & csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_initiate; always @(posedge CLK_I) csr_internal_trigger_rx_mem_regs_1_diag_cntrl_reg_initiate <= csr_internal_next_trigger_rx_mem_regs_1_diag_cntrl_reg_initiate; assign rx_mem_regs_1_diag_cntrl_reg_initiate_trigger = csr_internal_trigger_rx_mem_regs_1_diag_cntrl_reg_initiate; // Field: rx_mem_regs[1].diag_cntrl_reg.read // Position: [14] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_read = csr_internal_decode_rx_mem_regs_1_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_read = (csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_read) ? csr_internal_bus_write_data[14]: csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_read; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_read <= csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_read; assign rx_mem_regs_1_diag_cntrl_reg_read = csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_read; // Field: rx_mem_regs[1].diag_cntrl_reg.diagnostic_address // Position: [13:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address = csr_internal_decode_rx_mem_regs_1_diag_cntrl_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address = (csr_internal_write_access_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address) ? csr_internal_bus_write_data[13:0]: csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address <= csr_internal_next_field_rx_mem_regs_1_diag_cntrl_reg_diagnostic_address; // // Register: rx_mem_regs[1].ecc_bits_reg // Addressmap Offset: 0x2a0 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_ecc_bits_reg = { 10'h0, csr_internal_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits } & {16{csr_internal_decode_rx_mem_regs_1_ecc_bits_reg}}; // Field: rx_mem_regs[1].ecc_bits_reg.ecc_bits // Position: [5:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_ecc_bits_reg_ecc_bits = csr_internal_decode_rx_mem_regs_1_ecc_bits_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits = (csr_internal_write_access_rx_mem_regs_1_ecc_bits_reg_ecc_bits) ? csr_internal_bus_write_data[5:0]: (rx_mem_regs_1_ecc_bits_reg_ecc_bits_load_enable) ? rx_mem_regs_1_ecc_bits_reg_ecc_bits_input: csr_internal_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits; always @(posedge CLK_I or posedge RST_I) if (RST_I) csr_internal_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits <= 6'b0; else csr_internal_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits <= csr_internal_next_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits; assign rx_mem_regs_1_ecc_bits_reg_ecc_bits = csr_internal_field_rx_mem_regs_1_ecc_bits_reg_ecc_bits; // // Register: rx_mem_regs[1].data_reg // Addressmap Offset: 0x2c0 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_1_data_reg = csr_internal_field_rx_mem_regs_1_data_reg_data_value & {16{csr_internal_decode_rx_mem_regs_1_data_reg}}; // Field: rx_mem_regs[1].data_reg.data_value // Position: [15:0] // Access: read-write // Type: configuration assign csr_internal_write_access_rx_mem_regs_1_data_reg_data_value = csr_internal_decode_rx_mem_regs_1_data_reg & csr_internal_write_access; assign csr_internal_next_field_rx_mem_regs_1_data_reg_data_value = (csr_internal_write_access_rx_mem_regs_1_data_reg_data_value) ? csr_internal_bus_write_data: (rx_mem_regs_1_data_reg_data_value_load_enable) ? rx_mem_regs_1_data_reg_data_value_input: csr_internal_field_rx_mem_regs_1_data_reg_data_value; always @(posedge CLK_I) csr_internal_field_rx_mem_regs_1_data_reg_data_value <= csr_internal_next_field_rx_mem_regs_1_data_reg_data_value; // // Register: rx_mem_regs[2].ecc_cntrl_reg // Addressmap Offset: 0x300 // Access: read-write // assign csr_internal_read_data_rx_mem_regs_2_ecc_cntrl_reg = { 14'h0, csr_internal_field_rx_mem