`timescale 1s / 1s module ECC_regs_configuration_diag(); reg [7:0] expected_8bit_lsb_0; reg [15:0] expected_16bit_lsb_0; reg [31:0] expected_32bit_lsb_0; reg [63:0] expected_64bit_lsb_0; reg [127:0] expected_128bit_lsb_0; reg [0:7] expected_8bit_msb_0; reg [0:15] expected_16bit_msb_0; reg [0:31] expected_32bit_msb_0; reg [0:63] expected_64bit_msb_0; reg [0:127] expected_128bit_msb_0; reg [15:0] readDataValue; reg [15:0] designated_readDataValue; reg [15:0] tmpCsr; integer chkAddressError; integer chkReadAccessError; integer chkWriteAccessError; integer loopCount; always @(negedge ECC_regs_testbench.RST_I) begin: sim_block chkAddressError = 0; chkReadAccessError = 0; chkWriteAccessError = 0; $display("%d Enable write_enable for registers/fields", $time); $display("%d Start test for Configuration type fields - value of allZeros", $time); $display("%d CSR: chip_config", $time); writeOp(16'h0, {15'h0, 1'h0}); writeOp(16'h80, ~{15'h0, 1'h0}); expected_16bit_lsb_0 = {15'h0, 1'h0}; readOp(16'h0, readDataValue); expected_16bit_lsb_0[15:1] = 0; if (expected_16bit_lsb_0[15:1] !== readDataValue[15:1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:1], readDataValue[15:1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: pckt_mem_regs_ecc_cntrl_reg", $time); writeOp(16'h80, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h80, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: pckt_mem_regs_ecc_int_en_reg", $time); writeOp(16'h98, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h98, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: pckt_mem_regs_ecc_err_addr_reg", $time); writeOp(16'h9c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h9c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: pckt_mem_regs_diag_cntrl_reg", $time); writeOp(16'h9e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h9e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: pckt_mem_regs_ecc_bits_reg", $time); writeOp(16'ha0, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'ha0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: pckt_mem_regs_data_reg", $time); writeOp(16'hc0, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'hc0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_3_ecc_cntrl_reg", $time); writeOp(16'h380, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h380, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_3_ecc_int_en_reg", $time); writeOp(16'h398, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h398, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_3_ecc_err_addr_reg", $time); writeOp(16'h39c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h39c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_3_diag_cntrl_reg", $time); writeOp(16'h39e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h39e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_3_ecc_bits_reg", $time); writeOp(16'h3a0, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h3a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_3_data_reg", $time); writeOp(16'h3c0, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h3c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_2_ecc_cntrl_reg", $time); writeOp(16'h300, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h300, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_2_ecc_int_en_reg", $time); writeOp(16'h318, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h318, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_2_ecc_err_addr_reg", $time); writeOp(16'h31c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h31c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_2_diag_cntrl_reg", $time); writeOp(16'h31e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h31e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_2_ecc_bits_reg", $time); writeOp(16'h320, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h320, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_2_data_reg", $time); writeOp(16'h340, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h340, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_1_ecc_cntrl_reg", $time); writeOp(16'h280, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h280, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_1_ecc_int_en_reg", $time); writeOp(16'h298, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h298, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_1_ecc_err_addr_reg", $time); writeOp(16'h29c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h29c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_1_diag_cntrl_reg", $time); writeOp(16'h29e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h29e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_1_ecc_bits_reg", $time); writeOp(16'h2a0, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h2a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_1_data_reg", $time); writeOp(16'h2c0, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h2c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_0_ecc_cntrl_reg", $time); writeOp(16'h200, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h200, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_0_ecc_int_en_reg", $time); writeOp(16'h218, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h218, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_0_ecc_err_addr_reg", $time); writeOp(16'h21c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h21c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_0_diag_cntrl_reg", $time); writeOp(16'h21e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h21e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_0_ecc_bits_reg", $time); writeOp(16'h220, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h220, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_0_data_reg", $time); writeOp(16'h240, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h240, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_3_ecc_cntrl_reg", $time); writeOp(16'h580, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h580, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_3_ecc_int_en_reg", $time); writeOp(16'h598, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h598, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_3_ecc_err_addr_reg", $time); writeOp(16'h59c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h59c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: tx_mem_regs_3_diag_cntrl_reg", $time); writeOp(16'h59e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h59e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: tx_mem_regs_3_ecc_bits_reg", $time); writeOp(16'h5a0, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h5a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: tx_mem_regs_3_data_reg", $time); writeOp(16'h5c0, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h5c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_2_ecc_cntrl_reg", $time); writeOp(16'h500, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h500, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_2_ecc_int_en_reg", $time); writeOp(16'h518, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h518, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_2_ecc_err_addr_reg", $time); writeOp(16'h51c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h51c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: tx_mem_regs_2_diag_cntrl_reg", $time); writeOp(16'h51e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h51e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: tx_mem_regs_2_ecc_bits_reg", $time); writeOp(16'h520, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h520, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: tx_mem_regs_2_data_reg", $time); writeOp(16'h540, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h540, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_1_ecc_cntrl_reg", $time); writeOp(16'h480, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h480, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_1_ecc_int_en_reg", $time); writeOp(16'h498, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h498, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_1_ecc_err_addr_reg", $time); writeOp(16'h49c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h49c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: tx_mem_regs_1_diag_cntrl_reg", $time); writeOp(16'h49e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_1_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h49e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_1_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: tx_mem_regs_1_ecc_bits_reg", $time); writeOp(16'h4a0, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h4a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: tx_mem_regs_1_data_reg", $time); writeOp(16'h4c0, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h4c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_0_ecc_cntrl_reg", $time); writeOp(16'h400, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h400, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_0_ecc_int_en_reg", $time); writeOp(16'h418, {14'h0, 1'h0, 1'h0}); writeOp(16'h0, ~{14'h0, 1'h0, 1'h0}); expected_16bit_lsb_0 = {14'h0, 1'h0, 1'h0}; readOp(16'h418, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_0_ecc_err_addr_reg", $time); writeOp(16'h41c, {2'h0, 14'h0}); writeOp(16'h0, ~{2'h0, 14'h0}); expected_16bit_lsb_0 = {2'h0, 14'h0}; readOp(16'h41c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: tx_mem_regs_0_diag_cntrl_reg", $time); writeOp(16'h41e, {1'h0, 1'h0, 14'h0}); writeOp(16'h0, ~{1'h0, 1'h0, 14'h0}); expected_16bit_lsb_0 = {1'h0, 1'h0, 14'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_0_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h41e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_0_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: tx_mem_regs_0_ecc_bits_reg", $time); writeOp(16'h420, {10'h0, 6'h0}); writeOp(16'h0, ~{10'h0, 6'h0}); expected_16bit_lsb_0 = {10'h0, 6'h0}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h420, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: tx_mem_regs_0_data_reg", $time); writeOp(16'h440, {16'h0}); writeOp(16'h0, ~{16'h0}); expected_16bit_lsb_0 = {16'h0}; readOp(16'h440, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d Enable write_enable for registers/fields", $time); $display("%d Start test for Configuration type fields - value of random", $time); $display("%d CSR: chip_config", $time); writeOp(16'h0, {15'h0, 1'h1}); expected_16bit_lsb_0 = {15'h0, 1'h1}; readOp(16'h0, readDataValue); expected_16bit_lsb_0[15:1] = 0; if (expected_16bit_lsb_0[15:1] !== readDataValue[15:1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:1], readDataValue[15:1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end writeOp(16'h0, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; $display("%d CSR: pckt_mem_regs_ecc_cntrl_reg", $time); writeOp(16'h80, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h80, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h80, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: pckt_mem_regs_ecc_int_en_reg", $time); writeOp(16'h98, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h98, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: pckt_mem_regs_ecc_err_addr_reg", $time); writeOp(16'h9c, {2'h0, 14'hfff}); expected_16bit_lsb_0 = {2'h0, 14'hfff}; readOp(16'h9c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: pckt_mem_regs_diag_cntrl_reg", $time); writeOp(16'h9e, {1'h1, 1'h1, 14'h555}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'h555}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h9e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: pckt_mem_regs_ecc_bits_reg", $time); writeOp(16'ha0, {10'h0, 6'h15}); expected_16bit_lsb_0 = {10'h0, 6'h15}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'ha0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'ha0, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.pckt_mem_regs_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: pckt_mem_regs_data_reg", $time); writeOp(16'hc0, {16'h1555}); expected_16bit_lsb_0 = {16'h1555}; readOp(16'hc0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_3_ecc_cntrl_reg", $time); writeOp(16'h380, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h380, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h380, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_3_ecc_int_en_reg", $time); writeOp(16'h398, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h398, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_3_ecc_err_addr_reg", $time); writeOp(16'h39c, {2'h0, 14'hccc}); expected_16bit_lsb_0 = {2'h0, 14'hccc}; readOp(16'h39c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_3_diag_cntrl_reg", $time); writeOp(16'h39e, {1'h1, 1'h1, 14'h492}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'h492}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h39e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_3_ecc_bits_reg", $time); writeOp(16'h3a0, {10'h0, 6'ha}); expected_16bit_lsb_0 = {10'h0, 6'ha}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h3a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'h3a0, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_3_data_reg", $time); writeOp(16'h3c0, {16'hffff}); expected_16bit_lsb_0 = {16'hffff}; readOp(16'h3c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_2_ecc_cntrl_reg", $time); writeOp(16'h300, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h300, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h300, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_2_ecc_int_en_reg", $time); writeOp(16'h318, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h318, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_2_ecc_err_addr_reg", $time); writeOp(16'h31c, {2'h0, 14'h5d1}); expected_16bit_lsb_0 = {2'h0, 14'h5d1}; readOp(16'h31c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_2_diag_cntrl_reg", $time); writeOp(16'h31e, {1'h1, 1'h1, 14'h5d1}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'h5d1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h31e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_2_ecc_bits_reg", $time); writeOp(16'h320, {10'h0, 6'h1f}); expected_16bit_lsb_0 = {10'h0, 6'h1f}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h320, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'h320, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_2_data_reg", $time); writeOp(16'h340, {16'h1249}); expected_16bit_lsb_0 = {16'h1249}; readOp(16'h340, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_1_ecc_cntrl_reg", $time); writeOp(16'h280, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h280, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h280, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_1_ecc_int_en_reg", $time); writeOp(16'h298, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h298, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_1_ecc_err_addr_reg", $time); writeOp(16'h29c, {2'h0, 14'h666}); expected_16bit_lsb_0 = {2'h0, 14'h666}; readOp(16'h29c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_1_diag_cntrl_reg", $time); writeOp(16'h29e, {1'h1, 1'h1, 14'h7ff}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'h7ff}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h29e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_1_ecc_bits_reg", $time); writeOp(16'h2a0, {10'h0, 6'h1f}); expected_16bit_lsb_0 = {10'h0, 6'h1f}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h2a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'h2a0, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_1_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_1_data_reg", $time); writeOp(16'h2c0, {16'h2492}); expected_16bit_lsb_0 = {16'h2492}; readOp(16'h2c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: rx_mem_regs_0_ecc_cntrl_reg", $time); writeOp(16'h200, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h200, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h200, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: rx_mem_regs_0_ecc_int_en_reg", $time); writeOp(16'h218, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h218, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: rx_mem_regs_0_ecc_err_addr_reg", $time); writeOp(16'h21c, {2'h0, 14'h492}); expected_16bit_lsb_0 = {2'h0, 14'h492}; readOp(16'h21c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: rx_mem_regs_0_diag_cntrl_reg", $time); writeOp(16'h21e, {1'h1, 1'h1, 14'h4ec}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'h4ec}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h21e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: rx_mem_regs_0_ecc_bits_reg", $time); writeOp(16'h220, {10'h0, 6'h1f}); expected_16bit_lsb_0 = {10'h0, 6'h1f}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h220, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'h220, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.rx_mem_regs_0_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: rx_mem_regs_0_data_reg", $time); writeOp(16'h240, {16'h2aaa}); expected_16bit_lsb_0 = {16'h2aaa}; readOp(16'h240, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_3_ecc_cntrl_reg", $time); writeOp(16'h580, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h580, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h580, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_3_ecc_int_en_reg", $time); writeOp(16'h598, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h598, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_3_ecc_err_addr_reg", $time); writeOp(16'h59c, {2'h0, 14'h924}); expected_16bit_lsb_0 = {2'h0, 14'h924}; readOp(16'h59c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: tx_mem_regs_3_diag_cntrl_reg", $time); writeOp(16'h59e, {1'h1, 1'h1, 14'h3fff}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'h3fff}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h59e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: tx_mem_regs_3_ecc_bits_reg", $time); writeOp(16'h5a0, {10'h0, 6'hf}); expected_16bit_lsb_0 = {10'h0, 6'hf}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h5a0, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'h5a0, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_3_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: tx_mem_regs_3_data_reg", $time); writeOp(16'h5c0, {16'h2492}); expected_16bit_lsb_0 = {16'h2492}; readOp(16'h5c0, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_2_ecc_cntrl_reg", $time); writeOp(16'h500, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h500, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h500, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_2_ecc_int_en_reg", $time); writeOp(16'h518, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h518, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_2_ecc_err_addr_reg", $time); writeOp(16'h51c, {2'h0, 14'h4ec}); expected_16bit_lsb_0 = {2'h0, 14'h4ec}; readOp(16'h51c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:14], readDataValue[15:14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end $display("%d CSR: tx_mem_regs_2_diag_cntrl_reg", $time); writeOp(16'h51e, {1'h1, 1'h1, 14'hccc}); expected_16bit_lsb_0 = {1'h1, 1'h1, 14'hccc}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end readOp(16'h51e, readDataValue); if (expected_16bit_lsb_0[15] !== readDataValue[15]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15], readDataValue[15]); end if (expected_16bit_lsb_0[14] !== readDataValue[14]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[14], readDataValue[14]); end if (expected_16bit_lsb_0[13:0] !== readDataValue[13:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[13:0], readDataValue[13:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[14] !== ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_diag_cntrl_reg_read[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_diag_cntrl_reg_read[0], expected_16bit_lsb_0[14]); end $display("%d CSR: tx_mem_regs_2_ecc_bits_reg", $time); writeOp(16'h520, {10'h0, 6'ha}); expected_16bit_lsb_0 = {10'h0, 6'ha}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end readOp(16'h520, readDataValue); expected_16bit_lsb_0[15:6] = 0; if (expected_16bit_lsb_0[15:6] !== readDataValue[15:6]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:6], readDataValue[15:6]); end if (expected_16bit_lsb_0[5:0] !== readDataValue[5:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[5:0], readDataValue[5:0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end writeOp(16'h520, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[5:0] !== ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_2_ecc_bits_reg_ecc_bits[5:0], expected_16bit_lsb_0[5:0]); end $display("%d CSR: tx_mem_regs_2_data_reg", $time); writeOp(16'h540, {16'h1999}); expected_16bit_lsb_0 = {16'h1999}; readOp(16'h540, readDataValue); if (expected_16bit_lsb_0[15:0] !== readDataValue[15:0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:0], readDataValue[15:0]); end $display("%d CSR: tx_mem_regs_1_ecc_cntrl_reg", $time); writeOp(16'h480, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end readOp(16'h480, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end writeOp(16'h480, ~(16'h0)); #20; ECC_regs_testbench.RST_I = 1'b1; #20; ECC_regs_testbench.RST_I = 1'b0; repeat (5) @(posedge ECC_regs_testbench.CLK_I); expected_16bit_lsb_0 = 16'h0; @(posedge ECC_regs_testbench.CLK_I); if (expected_16bit_lsb_0[1] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_diag_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_diag_en[0], expected_16bit_lsb_0[1]); end if (expected_16bit_lsb_0[0] !== ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0]) begin $display("%d ERROR - Value of Output port tx_mem_regs_1_ecc_cntrl_reg_correct_en[0] different than expected value; %h != %h", $time, ECC_regs_testbench.tx_mem_regs_1_ecc_cntrl_reg_correct_en[0], expected_16bit_lsb_0[0]); end $display("%d CSR: tx_mem_regs_1_ecc_int_en_reg", $time); writeOp(16'h498, {14'h0, 1'h1, 1'h1}); expected_16bit_lsb_0 = {14'h0, 1'h1, 1'h1}; readOp(16'h498, readDataValue); expected_16bit_lsb_0[15:2] = 0; if (expected_16bit_lsb_0[15:2] !== readDataValue[15:2]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[15:2], readDataValue[15:2]); end if (expected_16bit_lsb_0[1] !== readDataValue[1]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[1], readDataValue[1]); end if (expected_16bit_lsb_0[0] !== readDataValue[0]) begin $display("%d ERROR - Expected value: %h, actual value: %h", $time, expected_16bit_lsb_0[0], readDataValue[0]); end $display("%d CSR: tx_mem_regs_1_ecc_err_addr_reg", $time); writeOp(16'h49c, {2'h0, 14'h1fff}); expected_16bit_lsb_0 = {2'h0, 14'h1fff}; readOp(16'h49c, readDataValue); expected_16bit_lsb_0[15:14] = 0; if (expected_16bit_lsb_0[15:14] !== readDataValue[15:14]) begin $display("%d ERROR - Expected value: %h, actual value: %h",