`timescale 1s / 1s

module ECC_regs_counter_diag();

reg [7:0] expected_8bit_lsb_0;
reg [15:0] expected_16bit_lsb_0;
reg [31:0] expected_32bit_lsb_0;
reg [63:0] expected_64bit_lsb_0;
reg [127:0] expected_128bit_lsb_0;
reg [0:7] expected_8bit_msb_0;
reg [0:15] expected_16bit_msb_0;
reg [0:31] expected_32bit_msb_0;
reg [0:63] expected_64bit_msb_0;
reg [0:127] expected_128bit_msb_0;
reg [15:0] readDataValue;
reg [15:0] designated_readDataValue;
reg [15:0] tmpCsr;
integer  chkAddressError;
integer  chkReadAccessError;
integer  chkWriteAccessError;
integer  loopCount;
reg [15:0] tmpCounterValue;
reg [15:0] numIncrCycles;
reg [15:0] numDecrCycles;
reg [15:0] maxCountValue;
reg [15:0] incrAmount;
reg [15:0] decrAmount;
reg [15:0] counterInitVal;

always @(negedge ECC_regs_testbench.RST_I) begin: sim_block
  chkAddressError = 0;
  chkReadAccessError = 0;
  chkWriteAccessError = 0;

  $display("%d Start test for Counter type fields", $time);

  $display("%d Initialize Register: pckt_mem_regs_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h82, readDataValue);

  $display("%d Initialize Register: rx_mem_regs_3_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h382, readDataValue);

  $display("%d Initialize Register: rx_mem_regs_2_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h302, readDataValue);

  $display("%d Initialize Register: rx_mem_regs_1_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h282, readDataValue);

  $display("%d Initialize Register: rx_mem_regs_0_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h202, readDataValue);

  $display("%d Initialize Register: tx_mem_regs_3_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h582, readDataValue);

  $display("%d Initialize Register: tx_mem_regs_2_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h502, readDataValue);

  $display("%d Initialize Register: tx_mem_regs_1_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h482, readDataValue);

  $display("%d Initialize Register: tx_mem_regs_0_ecc_int_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h402, readDataValue);
  $display("%d CSR: pckt_mem_regs_int_cnt_reg", $time);

  $display("%d Initialize Register: pckt_mem_regs_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h9a, readDataValue);

  $display("%d Counter field pckt_mem_regs_int_cnt_reg_sbe_int_cnt of register pckt_mem_regs_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field pckt_mem_regs_int_cnt_reg_sbe_int_cnt of pckt_mem_regs_int_cnt_reg register

  $display("%d Initialize Register: pckt_mem_regs_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h98, readDataValue);
  
  $display("%d field: pckt_mem_regs_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: pckt_mem_regs_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h98, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h98, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h9a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h9a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: pckt_mem_regs_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h9a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h9a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field pckt_mem_regs_int_cnt_reg_sbe_int_cnt of pckt_mem_regs_int_cnt_reg register

  $display("%d Initialize Register: pckt_mem_regs_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h98, readDataValue);
  
  $display("%d field: pckt_mem_regs_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: pckt_mem_regs_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h98, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h98, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h9a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field pckt_mem_regs_int_cnt_reg_mbe_int_cnt of register pckt_mem_regs_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field pckt_mem_regs_int_cnt_reg_mbe_int_cnt of pckt_mem_regs_int_cnt_reg register

  $display("%d Initialize Register: pckt_mem_regs_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h98, readDataValue);
  
  $display("%d field: pckt_mem_regs_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: pckt_mem_regs_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h98, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h98, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h9a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h9a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: pckt_mem_regs_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h9a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h9a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field pckt_mem_regs_int_cnt_reg_mbe_int_cnt of pckt_mem_regs_int_cnt_reg register

  $display("%d Initialize Register: pckt_mem_regs_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h98, readDataValue);
  
  $display("%d field: pckt_mem_regs_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: pckt_mem_regs_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h98, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h98, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.pckt_mem_regs_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h9a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h9a, readDataValue);
  $display("%d CSR: rx_mem_regs_3_int_cnt_reg", $time);

  $display("%d Initialize Register: rx_mem_regs_3_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h39a, readDataValue);

  $display("%d Counter field rx_mem_regs_3_int_cnt_reg_sbe_int_cnt of register rx_mem_regs_3_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_3_int_cnt_reg_sbe_int_cnt of rx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h318, readDataValue);
  
  $display("%d field: rx_mem_regs_3_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_3_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h318, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h318, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h39a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h39a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_3_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h39a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h39a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_3_int_cnt_reg_sbe_int_cnt of rx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h298, readDataValue);
  
  $display("%d field: rx_mem_regs_3_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_3_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h298, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h298, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h39a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field rx_mem_regs_3_int_cnt_reg_mbe_int_cnt of register rx_mem_regs_3_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_3_int_cnt_reg_mbe_int_cnt of rx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h218, readDataValue);
  
  $display("%d field: rx_mem_regs_3_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_3_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h218, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h218, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h39a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h39a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_3_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h39a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h39a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_3_int_cnt_reg_mbe_int_cnt of rx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: rx_mem_regs_3_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_3_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h39a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h39a, readDataValue);
  $display("%d CSR: rx_mem_regs_2_int_cnt_reg", $time);

  $display("%d Initialize Register: rx_mem_regs_2_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h31a, readDataValue);

  $display("%d Counter field rx_mem_regs_2_int_cnt_reg_sbe_int_cnt of register rx_mem_regs_2_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_2_int_cnt_reg_sbe_int_cnt of rx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h318, readDataValue);
  
  $display("%d field: rx_mem_regs_2_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_2_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h318, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h318, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h31a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h31a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_2_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h31a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h31a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_2_int_cnt_reg_sbe_int_cnt of rx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h298, readDataValue);
  
  $display("%d field: rx_mem_regs_2_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_2_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h298, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h298, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h31a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field rx_mem_regs_2_int_cnt_reg_mbe_int_cnt of register rx_mem_regs_2_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_2_int_cnt_reg_mbe_int_cnt of rx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h218, readDataValue);
  
  $display("%d field: rx_mem_regs_2_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_2_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h218, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h218, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h31a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h31a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_2_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h31a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h31a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_2_int_cnt_reg_mbe_int_cnt of rx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: rx_mem_regs_2_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_2_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h31a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h31a, readDataValue);
  $display("%d CSR: rx_mem_regs_1_int_cnt_reg", $time);

  $display("%d Initialize Register: rx_mem_regs_1_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h29a, readDataValue);

  $display("%d Counter field rx_mem_regs_1_int_cnt_reg_sbe_int_cnt of register rx_mem_regs_1_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_1_int_cnt_reg_sbe_int_cnt of rx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h318, readDataValue);
  
  $display("%d field: rx_mem_regs_1_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_1_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h318, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h318, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h29a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h29a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_1_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h29a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h29a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_1_int_cnt_reg_sbe_int_cnt of rx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h298, readDataValue);
  
  $display("%d field: rx_mem_regs_1_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_1_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h298, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h298, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h29a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field rx_mem_regs_1_int_cnt_reg_mbe_int_cnt of register rx_mem_regs_1_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_1_int_cnt_reg_mbe_int_cnt of rx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h218, readDataValue);
  
  $display("%d field: rx_mem_regs_1_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_1_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h218, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h218, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h29a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h29a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_1_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h29a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h29a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_1_int_cnt_reg_mbe_int_cnt of rx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: rx_mem_regs_1_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_1_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h29a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h29a, readDataValue);
  $display("%d CSR: rx_mem_regs_0_int_cnt_reg", $time);

  $display("%d Initialize Register: rx_mem_regs_0_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h21a, readDataValue);

  $display("%d Counter field rx_mem_regs_0_int_cnt_reg_sbe_int_cnt of register rx_mem_regs_0_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_0_int_cnt_reg_sbe_int_cnt of rx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h318, readDataValue);
  
  $display("%d field: rx_mem_regs_0_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_0_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h318, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h318, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h21a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h21a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_0_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h21a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h21a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_0_int_cnt_reg_sbe_int_cnt of rx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h298, readDataValue);
  
  $display("%d field: rx_mem_regs_0_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_0_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h298, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h298, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h21a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field rx_mem_regs_0_int_cnt_reg_mbe_int_cnt of register rx_mem_regs_0_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field rx_mem_regs_0_int_cnt_reg_mbe_int_cnt of rx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h218, readDataValue);
  
  $display("%d field: rx_mem_regs_0_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_0_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h218, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h218, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h21a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h21a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: rx_mem_regs_0_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h21a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h21a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field rx_mem_regs_0_int_cnt_reg_mbe_int_cnt of rx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: rx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: rx_mem_regs_0_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: rx_mem_regs_0_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.rx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h21a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h21a, readDataValue);
  $display("%d CSR: tx_mem_regs_3_int_cnt_reg", $time);

  $display("%d Initialize Register: tx_mem_regs_3_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h59a, readDataValue);

  $display("%d Counter field tx_mem_regs_3_int_cnt_reg_sbe_int_cnt of register tx_mem_regs_3_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_3_int_cnt_reg_sbe_int_cnt of tx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h518, readDataValue);
  
  $display("%d field: tx_mem_regs_3_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_3_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h518, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h518, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h59a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h59a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_3_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h59a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h59a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_3_int_cnt_reg_sbe_int_cnt of tx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h498, readDataValue);
  
  $display("%d field: tx_mem_regs_3_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_3_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h498, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h498, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h59a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field tx_mem_regs_3_int_cnt_reg_mbe_int_cnt of register tx_mem_regs_3_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_3_int_cnt_reg_mbe_int_cnt of tx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: tx_mem_regs_3_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_3_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h59a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h59a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_3_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h59a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h59a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_3_int_cnt_reg_mbe_int_cnt of tx_mem_regs_3_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h618, readDataValue);
  
  $display("%d field: tx_mem_regs_3_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_3_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h618, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h618, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_3_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h59a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h59a, readDataValue);
  $display("%d CSR: tx_mem_regs_2_int_cnt_reg", $time);

  $display("%d Initialize Register: tx_mem_regs_2_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h51a, readDataValue);

  $display("%d Counter field tx_mem_regs_2_int_cnt_reg_sbe_int_cnt of register tx_mem_regs_2_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_2_int_cnt_reg_sbe_int_cnt of tx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h518, readDataValue);
  
  $display("%d field: tx_mem_regs_2_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_2_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h518, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h518, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h51a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h51a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_2_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h51a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h51a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_2_int_cnt_reg_sbe_int_cnt of tx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h498, readDataValue);
  
  $display("%d field: tx_mem_regs_2_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_2_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h498, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h498, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h51a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field tx_mem_regs_2_int_cnt_reg_mbe_int_cnt of register tx_mem_regs_2_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_2_int_cnt_reg_mbe_int_cnt of tx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: tx_mem_regs_2_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_2_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h51a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h51a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_2_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h51a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h51a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_2_int_cnt_reg_mbe_int_cnt of tx_mem_regs_2_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h618, readDataValue);
  
  $display("%d field: tx_mem_regs_2_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_2_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h618, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h618, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_2_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h51a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h51a, readDataValue);
  $display("%d CSR: tx_mem_regs_1_int_cnt_reg", $time);

  $display("%d Initialize Register: tx_mem_regs_1_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h49a, readDataValue);

  $display("%d Counter field tx_mem_regs_1_int_cnt_reg_sbe_int_cnt of register tx_mem_regs_1_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_1_int_cnt_reg_sbe_int_cnt of tx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h518, readDataValue);
  
  $display("%d field: tx_mem_regs_1_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_1_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h518, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h518, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h49a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h49a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_1_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h49a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h49a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_1_int_cnt_reg_sbe_int_cnt of tx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h498, readDataValue);
  
  $display("%d field: tx_mem_regs_1_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_1_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h498, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h498, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h49a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field tx_mem_regs_1_int_cnt_reg_mbe_int_cnt of register tx_mem_regs_1_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_1_int_cnt_reg_mbe_int_cnt of tx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: tx_mem_regs_1_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_1_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h49a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h49a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_1_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h49a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h49a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_1_int_cnt_reg_mbe_int_cnt of tx_mem_regs_1_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h618, readDataValue);
  
  $display("%d field: tx_mem_regs_1_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_1_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h618, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h618, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_1_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h49a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h49a, readDataValue);
  $display("%d CSR: tx_mem_regs_0_int_cnt_reg", $time);

  $display("%d Initialize Register: tx_mem_regs_0_int_cnt_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h41a, readDataValue);

  $display("%d Counter field tx_mem_regs_0_int_cnt_reg_sbe_int_cnt of register tx_mem_regs_0_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_0_int_cnt_reg_sbe_int_cnt of tx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_2_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h518, readDataValue);
  
  $display("%d field: tx_mem_regs_0_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_0_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h518, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h518, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h41a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end
  expected_16bit_lsb_0[15:8] = 0;
  readOp(16'h41a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_0_int_cnt_reg_sbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h41a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[15:8] = 8'hff;
  writeOp(16'h41a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_0_int_cnt_reg_sbe_int_cnt of tx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_1_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h498, readDataValue);
  
  $display("%d field: tx_mem_regs_0_ecc_int_reg_sbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_0_ecc_int_reg_sbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h498, readDataValue);
  tmpCsr = 16'h2;
  readDataValue[1] = tmpCsr[1];
  writeOp(16'h498, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_sbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[15:8] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h41a, readDataValue);
  if (expected_16bit_lsb_0[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[15:8], readDataValue[15:8]);
  end


  $display("%d Counter field tx_mem_regs_0_int_cnt_reg_mbe_int_cnt of register tx_mem_regs_0_int_cnt_reg", $time);

  maxCountValue = 8'hff;
  numIncrCycles = 0;
  incrAmount = 8'b00000001;
  if (incrAmount !== 0) begin
    counterInitVal = 8'h0;
    numIncrCycles = (maxCountValue - counterInitVal)/incrAmount;
  end

  // Activate Counter field tx_mem_regs_0_int_cnt_reg_mbe_int_cnt of tx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_0_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h418, readDataValue);
  
  $display("%d field: tx_mem_regs_0_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_0_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h418, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h418, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h41a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end
  expected_16bit_lsb_0[7:0] = 0;
  readOp(16'h41a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  $display("%d Rollover of counter field: tx_mem_regs_0_int_cnt_reg_mbe_int_cnt", $time);

  $display("%d Write counter initial value(read/modify/write).", $time);

  readOp(16'h41a, readDataValue);
  tmpCounterValue = readDataValue;
  readDataValue[7:0] = 8'hff;
  writeOp(16'h41a, readDataValue);
  
  incrAmount = 8'b00000001;
  numIncrCycles = 1;
  counterInitVal = 8'hff;

  // Activate Counter field tx_mem_regs_0_int_cnt_reg_mbe_int_cnt of tx_mem_regs_0_int_cnt_reg register

  $display("%d Initialize Register: tx_mem_regs_4_ecc_int_en_reg", $time);

  readDataValue = 16'h0;
  writeOp(16'h618, readDataValue);
  
  $display("%d field: tx_mem_regs_0_ecc_int_reg_mbe_int", $time);
  $display("Register has hierarchical int: 0, hierarchical int. has enable: 0, enable hierarchical int: 1");
  $display("Register has interrupt_enable_port: 0, enable register_interrupt_enable port: 0");
  $display("status int. has enable: 1, enable status int: 1, status int. flag: 1");

  $display("%d Enable interrupt; field: tx_mem_regs_0_ecc_int_reg_mbe_int", $time);

  $display("%d Generate Read/Modify/Write op.", $time);
  readOp(16'h618, readDataValue);
  tmpCsr = 16'h1;
  readDataValue[0] = tmpCsr[0];
  writeOp(16'h618, readDataValue);
  @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h1;

  repeat (numIncrCycles) @(posedge ECC_regs_testbench.CLK_I);
  ECC_regs_testbench.tx_mem_regs_0_ecc_int_reg_mbe_int_source <= 1'h0;
  @(posedge ECC_regs_testbench.CLK_I);
  expected_16bit_lsb_0[7:0] = (incrAmount * numIncrCycles) + counterInitVal;
  
  readOp(16'h41a, readDataValue);
  if (expected_16bit_lsb_0[7:0] !== readDataValue[7:0]) begin
    $display("%d ERROR - Expected value: %h, actual value: %h",
              $time, expected_16bit_lsb_0[7:0], readDataValue[7:0]);
  end

  // Check for spillage into the next field

  if (tmpCounterValue[15:8] !== readDataValue[15:8]) begin
    $display("%d ERROR - Counter rolled over to next field.", $time);
    $display("%d Next field Expected value: %h, actual value: %h",
              $time, tmpCounterValue[15:8], readDataValue[15:8]);
  end

  readOp(16'h41a, readDataValue);
  $display("%d TEST FINISHED!", $time);
  #500; $finish;

end

task readOp;
  input[15:0] address;
  output[15:0] readDataValue;
  begin
    @(posedge ECC_regs_testbench.CLK_I);
    ECC_regs_testbench.ADR_I = address;
    ECC_regs_testbench.CYC_I = 1'b1;
    ECC_regs_testbench.STB_I = 1'b1;
    ECC_regs_testbench.WE_I = 1'b0;
    @(posedge ECC_regs_testbench.ACK_O);
    @(posedge ECC_regs_testbench.CLK_I);
    ECC_regs_testbench.STB_I = 1'b0;
    readDataValue = ECC_regs_testbench.DATA_O;
  end
endtask

task writeOp;
  input[15:0] address;
  input[15:0] writeData;
  begin
    @(posedge ECC_regs_testbench.CLK_I);
    ECC_regs_testbench.ADR_I = address;
    ECC_regs_testbench.CYC_I = 1'b1;
    ECC_regs_testbench.STB_I = 1'b1;
    ECC_regs_testbench.WE_I = 1'b1;
    ECC_regs_testbench.DATA_I = writeData;
    @(posedge ECC_regs_testbench.ACK_O);
    @(posedge ECC_regs_testbench.CLK_I);
    ECC_regs_testbench.STB_I = 1'b0;
  end
endtask

endmodule